Added readme_check_guideline.md along with the check_guideline.py
to explain the usage of this and to show how it should be used.
Signed-off-by: Iulia Moldovan <iulia.moldovan@analog.com>
Deleted lines after endmodule and consecutive empty lines.
Modified parentheses, extra spaces.
Fixed indentation.
Fixed parameters list to be each parameter on its line.
Signed-off-by: Iulia Moldovan <iulia.moldovan@analog.com>
* Added header license for the files that didn't have
* Modified parentheses
* Removed extra spaces at the end of lines
* Fixed parameters list to be each parameter on its line
* Deleted lines after endmodule and consecutive empty lines
* Fixed indentation
Signed-off-by: Iulia Moldovan <iulia.moldovan@analog.com>
* Updated action to run only in PRs on master branch, on library/ and
projects/ paths
* Edited the text for the printed warnings
* Updated the version for the checkout action from v2 to v3
Signed-off-by: Iulia Moldovan <iulia.moldovan@analog.com>
Added the files generated by Quartus Pro 21.2, 20.1 and Platform Designer for each of the versions. The files added are generated and removed by make.
Signed-off-by: Liviu.Iacob <liviu.iacob@analog.com>
- Added an utility buffer in order to generate the 50Mhz DRP clock.
- 'addn_ui_clockout4' will be used to generate the higher frequency 'sys_mb' clock for Microblaze.
Signed-off-by: Filip Gherman <Filip.Gherman@analog.com>
Increased the Microblaze performance for the VCU118 carrier:
- Increased the size of Instruction Cache and Data Cache to 64kB
Increased the Microblaze clock frequency:
- Using the DDR4 Controller to generate a new sys_mb_clk of 214 MHz to drive all the Microblaze interfaces at higher frequencies
Signed-off-by: Filip Gherman <Filip.Gherman@analog.com>
Almost all the IPs found in library generate a bd folder when they are built. Updated the .gitignore so that it does not appear as an untracked file.
Also, changes to tracked bd.tcl files (ex:axi_dmac) will still appear as modified files.
Signed-off-by: Liviu.Iacob <liviu.iacob@analog.com>
Created a virtual clock to constrain cnv_en.
Given that the cnv_en should be asserted only once per 8 clock
cycles and only the rise edge is of interest, we can constrain
the path as multicycle path.
Because the inferface signals which pass through the eval board's
Arduino connector are connected to level shifters the design
will not work at the maximum clk frequency of 48MHz. The maximum
tested frequency is 24MHz.
On architectures with ports that support cache coherency, the AWCACHE
signal must be set to indicate that transactions are cached. This patch
adds a parameter allowing AWCACHE to be set on an AXI4 destination port.
Laszlo Nagy
Filip Gherman
LIacob106
alin724
Iulia Moldovan
Laszlo Nagy
ladace
PopPaul2021
Ionut Podgoreanu
Adrian Costina
Benjamin Menkuec
AndreiGrozav
Stanca Pop
sergiu arpadi
Mathias Tausen
Morten Jensen