185e489802
cpack- signaltap mess
2015-06-29 16:31:53 -04:00
6862655b0d
Add .gitattributes file
...
Add .gitattributes file which sets up the eol encoding handling. This will
make sure that we get a uniform eol encoding across different operating
systems.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 11:07:10 +02:00
c0dd80ccee
axi_hdmi_rx: Fix alignment issue on packed formats
...
Some cases, when software changed the image formats, the packed formats (24bit/pixel) lost alignment.
(the first 32 bit after sof got lost) This commit fix that issue.
2015-06-24 12:43:55 +03:00
281a47c117
bsplit- altera version, avalon needs a clock
2015-06-24 05:31:08 -04:00
f4a1a5817c
jesd-align: allow sof pass through -- qsys can only do 1 src-dest
2015-06-24 05:31:06 -04:00
e1b1e1bc2c
ad9250- update to use alt ip interface script
2015-06-24 05:31:04 -04:00
00bc48bc24
axi_hdmi_rx: Fix synchronization issues
2015-06-24 11:03:39 +03:00
4e30a5b0bf
axi_ad9250: Updated altera core to work with axi4lite interface
2015-06-23 14:29:23 +03:00
3e5a5504a7
library/jesd-align- remove signaltap interface
2015-06-19 14:33:03 -04:00
af2ffbe0a0
library/cpack- add signaltap
2015-06-19 14:33:02 -04:00
ac6e28c461
library/common: add altera signaltap
2015-06-19 14:33:01 -04:00
8a52631189
libary: util_jesd_align- signal tap interface
2015-06-19 14:32:57 -04:00
7e08ff0422
library: added util_jesd_xmit
2015-06-19 14:32:56 -04:00
ad743c8403
axi_ad9434: This IP core does not have 'data underflow' port
2015-06-18 16:51:42 +03:00
d137811952
util_gmii_to_rgmii: Updated core so that it has an option to include a delay controller.
...
It also allows to configure the fixed delay value so that no additional constraints are needed
The default value of 18 seems to work very well(450mbps tx / 640 mbps rx) on the motor control platform used for tests
2015-06-16 17:39:31 +03:00
28e8275a5d
library/axi_jesd_gt: split gt lanes
2015-06-12 15:56:03 -04:00
ddc08c960c
ad_tdd_control: Connect the reset to all the flops
2015-06-11 12:07:47 +03:00
04eb998ff1
axi_jesd_gt: constraints
2015-06-10 14:29:06 -04:00
e2f4a4c5cf
library: make preset registered for timing paths
2015-06-10 13:41:41 -04:00
df0eaad1e2
gt: constraints
2015-06-10 11:38:15 -04:00
8a1f4bf5f6
ad6676,ad9144,ad9152,ad9234,ad9250,ad9434,ad9467,ad9625,ad652,ad9671,ad9680,ad9739a:Set default driver value for overflow, underflow, gpio_in and dac_sync ports
2015-06-09 14:21:12 +03:00
a598e1c614
axi_ad9265: Set default driver value for overflow and underflow ports
2015-06-08 17:50:23 +03:00
ccf887f0ba
axi_ad9643: Set default driver values for overflow, underflow and gpio_in ports
2015-06-08 17:48:41 +03:00
ded0dd5dbe
axi_ad9122: fixed constraints, removed unneded drp reset
2015-06-08 17:45:14 +03:00
c926daca3a
ad9361/tdd: Fix generation of tx_valid_* signals
...
In FDD mode the tx_valid_* signals are generated inside the axi_ad9361_tx module, in function of
the selected dac data rate. In TDD mode, these signals are gated by the tdd_enable and tdd_tx_dp_en signals.
In other words, the tx_valid_* signals will be valid just when tdd_enable and tdd_tx_dp_en is active.
2015-06-08 16:22:21 +03:00
ce60056cd5
wfifo: async reset for cpu side
2015-06-05 12:44:04 -04:00
ab1f9bed10
wfifo: remove srl from sync registers
2015-06-05 12:44:04 -04:00
da8915296b
pack: ip scripts
2015-06-05 09:20:08 -04:00
6338dfd8b7
ad9361: ip defaults & rst output
2015-06-05 09:19:39 -04:00
cb0324c2b1
wfifo: multi-channel option
2015-06-05 09:19:05 -04:00
2e877389b2
ad9361_tdd: Some naming and hierarchical changes
2015-06-04 18:09:49 +03:00
3b1ea7e528
axi_ad9361/tdd: Cherry picked commit 598ece4 from hdl_2015_r1 branch
...
598ece4c8d
2015-06-04 18:09:47 +03:00
6548bcd71f
axi_ip- constraints: add rst path
2015-06-04 10:53:13 -04:00
e02273781f
ad_rst- non lpm version
2015-06-04 10:53:12 -04:00
91b0f70972
library: remove drp cntrl
2015-06-02 09:58:57 -04:00
2b5abf74d7
util_upack: Show upack_valid only if the channel is activated
2015-06-02 11:36:06 +03:00
297e885981
library- drp moved to up-clock domain
2015-06-01 14:52:52 -04:00
e7470036bf
library- drp moved to up clock
2015-06-01 13:39:26 -04:00
c6ebab7393
library- drp moved to up clock
2015-06-01 13:39:26 -04:00
aa24c442f5
a10gx- no-ddr
2015-06-01 11:00:01 -04:00
d7b68c39ef
altera- sdc
2015-06-01 10:59:59 -04:00
2a0bdbebf2
altera- sdc
2015-06-01 10:59:58 -04:00
92fc0e050d
altera- common sdc
2015-06-01 10:59:57 -04:00
83df53d9bf
adc_common: Updated version because the delay registers have been changed
2015-05-25 17:18:14 +03:00
1ef83bd88b
axi_ad9671: Updated port names. Fixed synchronization of the rx_sof with the ad_jesd_align module, so that data valid is assigned correctly
2015-05-23 00:16:27 +03:00
660c84e01c
axi_ad9434 : Update the IO delay interface
2015-05-22 19:47:09 +03:00
0c6ef203c0
iobuf: do is a system-verilog keyword
2015-05-21 14:06:13 -04:00
dc2eeebf2f
upack: gen-name
2015-05-21 14:06:12 -04:00
5c6340e927
dmac: clock-typo
2015-05-21 14:06:11 -04:00
e05ff26406
ad9144: ddata-typo
2015-05-21 14:06:09 -04:00
Rejeesh Kutty
Lars-Peter Clausen
Istvan Csomortani
Adrian Costina