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10 Commits (334aaeb59a58bc53147cc9722f5586b771193a3d)

Author SHA1 Message Date
Istvan Csomortani 57cfb7cfb1 hdl/library: Update the IP parameters 
The following IP parameters were renamed:

PCORE_ID --> ID
PCORE_DEVTYPE --> DEVICE_TYPE
PCORE_IODELAY_GROUP --> IO_DELAY_GROUP
CH_DW --> CHANNEL_DATA_WIDTH
CH_CNT --> NUM_OF_CHANNELS
PCORE_BUFTYPE --> DEVICE_TYPE
PCORE_ADC_DP_DISABLE --> ADC_DATAPATH_DISABLE
CHID --> CHANNEL_ID
PCORE_DEVICE_TYPE --> DEVICE_TYPE
PCORE_MMCM_BUFIO_N --> MMCM_BUFIO_N
PCORE_SERDES_DDR_N --> SERDES_DDR_N
PCORE_DAC_DP_DISABLE --> DAC_DATAPATH_DISABLE
DP_DISABLE --> DATAPATH_DISABLE
PCORE_DAC_IODELAY_ENABLE --> DAC_IODELAY_ENABLE
C_BIG_ENDIAN --> BIG_ENDIAN
C_M_DATA_WIDTH --> MASTER_DATA_WIDTH
C_S_DATA_WIDTH --> SLAVE_DATA_WIDTH
NUM_CHANNELS --> NUM_OF_CHANNELS
CHANNELS --> NUM_OF_CHANNELS
PCORE_4L_2L_N -->QUAD_OR_DUAL_N
C_ADDRESS_WIDTH --> ADDRESS_WIDTH
C_DATA_WIDTH --> DATA_WIDTH
C_CLKS_ASYNC --> CLKS_ASYNC
PCORE_QUAD_DUAL_N --> QUAD_DUAL_N
NUM_CS --> NUM_OF_CS
PCORE_DAC_CHANNEL_ID --> DAC_CHANNEL_ID
PCORE_ADC_CHANNEL_ID --> ADC_CHANNEL_ID
PCORE_CLK0_DIV --> CLK0_DIV
PCORE_CLK1_DIV --> CLK1_DIV
PCORE_CLKIN_PERIOD --> CLKIN_PERIOD
PCORE_VCO_DIV --> VCO_DIV
PCORE_Cr_Cb_N --> CR_CB_N
PCORE_VCO_MUL --> VCO_MUL
PCORE_EMBEDDED_SYNC --> EMBEDDED_SYNC
PCORE_AXI_ID_WIDTH --> AXI_ID_WIDTH
PCORE_ADDR_WIDTH --> ADDRESS_WIDTH
DADATA_WIDTH --> DATA_WIDTH
NUM_OF_NUM_OF_CHANNEL --> NUM_OF_CHANNELS
DEBOUNCER_LEN --> DEBOUNCER_LENGTH
ADDR_WIDTH --> ADDRESS_WIDTH
C_S_AXIS_REGISTERED --> S_AXIS_REGISTERED
Cr_Cb_N --> CR_CB_N
ADDATA_WIDTH --> ADC_DATA_WIDTH
BUFTYPE --> DEVICE_TYPE
NUM_BITS --> NUM_OF_BITS
WIDTH_A --> A_DATA_WIDTH
WIDTH_B --> B_DATA_WIDTH
CH_OCNT --> NUM_OF_CHANNELS_O
M_CNT --> NUM_OF_CHANNELS_M
P_CNT --> NUM_OF_CHANNELS_P
CH_ICNT --> NUM_OF_CHANNELS_I
CH_MCNT --> NUM_OF_CHANNELS_M
4L_2L_N --> QUAD_OR_DUAL_N
SPI_CLK_ASYNC --> ASYNC_SPI_CLK
MMCM_BUFIO_N --> MMCM_OR_BUFIO_N
SERDES_DDR_N --> SERDES_OR_DDR_N
CLK_ASYNC --> ASYNC_CLK
CLKS_ASYNC --> ASYNC_CLK
SERDES --> SERDES_OR_DDR_N
GTH_GTX_N --> GTH_OR_GTX_N
IF_TYPE --> DDR_OR_SDR_N
PARALLEL_WIDTH --> DATA_WIDTH
ADD_SUB --> ADD_OR_SUB_N
A_WIDTH --> A_DATA_WIDTH
CONST_VALUE --> B_DATA_VALUE
IO_BASEADDR --> BASE_ADDRESS
IO_WIDTH --> DATA_WIDTH
QUAD_DUAL_N --> QUAD_OR_DUAL_N
AXI_ADDRLIMIT --> AXI_ADDRESS_LIMIT
ADDRESS_A_DATA_WIDTH --> A_ADDRESS_WIDTH
ADDRESS_B_DATA_WIDTH --> B_ADDRESS_WIDTH
MODE_OF_ENABLE --> CONTROL_TYPE
CONTROL_TYPE --> LEVEL_OR_PULSE_N
IQSEL --> Q_OR_I_N
MMCM --> MMCM_OR_BUFR_N
 2015-08-19 14:11:47 +03:00
Paul Cercueil e64baad54a axi_dmac: Fix a bug occuring on transfers < one beat 
Signed-off-by: Paul Cercueil <paul.cercueil@analog.com>
 2015-08-19 10:23:26 +02:00
Adrian Costina acde4f2c9a axi_dmac: Added fix to work with motor_control 2014-09-03 12:10:34 +03:00
Adrian Costina 58fa0776c9 axi_dmac: Added patch to fix issue on altera systems 2014-08-26 16:24:34 +03:00
Lars-Peter Clausen dc7b3e085c axi_dmac: Fix issues with non 64-bit AXI masters 
Make sure that the address generator behaves correctly when the buswidth is not
64-bit. Also since the source and destination can have different widths add
separate parameters for source and destination address alignment.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2014-04-10 14:54:22 +02:00
Lars-Peter Clausen 7ca43f4920 axi_dmac: address_generator: Make 'len' registered 
Slightly improves the timing.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2014-04-10 13:50:39 +02:00
Lars-Peter Clausen e373b85954 axi_dmac: Fix Vivado warnings 
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2014-03-18 20:59:13 +01:00
Lars-Peter Clausen f02ba999ae axi_dmac: Add support for DMA bus widths other than 64 bit 
There were a few place in the core where it assumed a 64-bit wide bus. Make this
configurable using parameters. The patch also adds support for having different
DMA bus widths on the source and destination side.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2014-03-13 13:20:10 +01:00
Lars-Peter Clausen 8326022adc axi_dmac: address_generator: Fix disable race condition 
If the address generator is disabled the very same cycle as it tries to put a
new address on the bus, it will keep sending this address forever and the core
will lock up

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2014-03-07 18:40:49 +01:00
Adrian Costina 831c19ea84 Added axi_dmac, axi_fifo and misc files in library 2014-03-06 18:16:02 +02:00