Instead of just marking all clock domains as asynchronous set the
appropriate constraints for each CDC path.
For single-bit synchronizers use set_false_path to not constraint the path
at at all.
For multi-bit synchronizers as used for gray counters use set_max_delay with
the source clock period domain to make sure that the signal skew will not
exceed one clock period. Otherwise one bit might overtake another and the
synchronizer no longer works correctly.
For multi-bit synchronizers implemented with hold registers use
set_max_delay with the target clock period to make sure that the skew does
not get to large, otherwise we might violate setup and hold time.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Bring back the AXIS FIFO as a separate module instead of embedding it into
the DMAC module. This makes it possible to use it in other modules outside
of the DMAC.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Move the axi_repack block to its own module. This allows it to use it
outside of the DMA controller.
Also rename it to util_axis_resize to better reflect its function.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Modify the adi_add_bus() function to take the full vlnv strings instead of just the bus type.
This makes the function more flexible and e.g. allows to handle buses from other vendors.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
When the DMA controller gets disabled in the middle of a transfer it is
possible that the resize block contains a partial sample. Starting the next
transfer the partial sample will appear the begining of the new stream and
also cause a channel shift.
To avoid this make sure to reset and flush the resize blocks when the DMA
controller is disabled.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
We need to make sure to not prematurely de-assert the s_valid signal for the
request splitter when disabling the DMAC. Otherwise it is possible that
under certain conditions the DMAC is disabled with a partially accepted
request and when it is enabled again it will continue in an inconsistent
state which can lead to transfer corruption or pipeline stalls.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
All components should use the internal 'do_enable' signal instead of the
external 'enable' signal. The former correctly incorporates the shutdown
sequence and does not get asserted again until the shutdown has been
completed. Using the external signal can cause problems when it is disabled
and enabled again in close proximity.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Currently when the DMAC gets disabled the request_generator will still
generate all remaining burst requests for the currently active transfer.
While these requests will be ignored by the source and destination component
this can still take a fair amount of time for long transfers.
So just stop generating burst requests once the DMAC is being disabled.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Refactor the fifo_inf modules to always correctly generate the underflow and
overflow status signals. Before it was possible that in some cases they
were not generated when they should have been.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Tcl command "if" is not supported by Vivado XDC, therefore the tool throw some critical warnings, and does not
apply the constraints, which can cause timing violations at case of some carriers.
The following solution is much more compact and is supported by the XDC, and more importantly prevents
unwanted critical errors and timing violations.
Vivado 2014.4 is too greedy, when it needs to optimize. See more about the issue here: https://ez.analog.com/thread/48214
The response_dest_resp is unused, so not save to concatenate with a valid signal like the eot.
This silences warnings from the tools about having no clock assigned to the bus.
Also fix the name of the TVALID signal.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
The dummy a{r,w}len fields should have the same width as the real a{w,r}len
fields in order to not break auto AXI bus version detection.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Clear the pipeline when no transfers are active to make sure that we do not
get residual data on the first sample for the next transfer.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
We can remove the Altera toplevel wrapper if we switch the axi4 control bus
to axi4lite and add the few missing signals that are required by the Altera
interconnect to both the control and the data buses.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
This is unused and unneeded. The AXI interconnect will make sure that a
peripheral only gets requests that are meant for it, there is no need to
check the address in the peripheral itself.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
We must make sure that the response ID is the same as the request ID when we
accepted the request. Otherwise we might respond with the wrong ID and the
system will lockup.
Also set rlast to 1 instead of 0.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Lars-Peter Clausen
Adrian Costina
Rejeesh Kutty
Istvan Csomortani