Removes a lot of boilerplate code.
Using the new scheme it is possible to add new projects or sub-projects
without having to re-generate any existing Makefiles.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
This reduces the amount of boilerplate code that is present in these
Makefiles by a lot.
It also makes it possible to update the Makefile rules in future without
having to re-generate all the Makefiles.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
The TX side runs on QPLL, and the RX and RX_OS runs on CPLL by default.
The OUTCLK frequency is the same as the REFCLK.
The main reason of this modification is that the links should come up
without any DPR access, after power up, using the default reference clock
configuration (122.88 MHz).
The constraint where added to remove timing problems on the reset path.
The constraint paths do not match anymore. The resets are used in a synchronous
way so we don't need the timing exceptions anyway.
Projects affected by this change:
- daq3
- adrv9739
- ad6676evb
- fmcadc5
- daq2/kcu105
- fmcadc2
- adrv9371x
- fmcomms11/zc706
- fmcjesdadc1
Make sure that the axi_adxcvr instances are configured with the same
transceiver type as the util_adxcvr.
This is necessary for software to be able to detect the transceiver type
and support dynamic reconfiguration.
It is also necessary for correct eye scan support in the axi_adxcvr block.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Fix the location assignment of the transceiver blocks to get the correct
lane mapping.
Note that the comments indicating the expected lane mapping are correct,
but the actual transceiver location assignments were not.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
The external reference clock runs at 122.88 MHz by default. This means that
the QPLL feedback divider needs to be set to 80 so that the VCO is inside
the locking range (9.8 GHz - 16.375 GHz).
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Currently the TX lane mapping is implemented by having to connect tx_phy_s_* to
the tx_ip_s_* and the tx_phy_d_* to the tx_ip_d_* signals in the system
qsys file in the desired order.
Re-work things so that instead the lane mapping is provided through the
TX_LANE_MAP parameter. The parameter specifies in which order logical lanes
are mapped onto the physical lanes.
The appropriate connections are than made inside the core according to this
parameter rather than having to manually connect the signals externally.
In order to generate a 1-to-1 mapping the TX_LANE_MAP parameter can be left
empty.
This change slightly reduces the boiler-plate code that is necessary to
setup the transceiver.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
The PLL frequency must be half of the lane rate and the core clock rate
must be lane rate divided by 40. There is no other option, otherwise things
wont work.
Instead of having to manually specify PLL and core clock frequency derive
them in the transceiver script. This reduces the risk of accidental
misconfiguration.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Qsys allows to query to query the clock domain that is associated with a
clock input of a peripheral. This allows to automatically detect whether
the different clocks of the DMAC are asynchronous and CDC logic needs to be
inserted or not.
Auto-detection has the advantages that the configuration parameters don't
need to be set manually and the optional configuration will be choose
automatically. There is also less chance of error of leaving the settings
in a wrong configuration when e.g. the clock domains change.
In case the auto-detection should ever fail configuration options that
provide a manual overwrite are added as well.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Lars-Peter Clausen
Istvan Csomortani
AndreiGrozav
Adrian Costina
Michael Hennerich
Rejeesh Kutty