Commit Graph

2847 Commits (35d32e01438dd79a5e97f0d95643ad88d335f2c6)

Author SHA1 Message Date
Laszlo Nagy 35d32e0143 util_do_ram: Initial version
This IP replaces the ad_mem_asym module as storage element for the data
offload.
Having standard AXIS interface for data will allow
implementation of storages on UltraRAM.
2022-04-28 14:31:32 +03:00
Laszlo Nagy 3209b9d840 interfaces: Data offload control interface
Have a control interface between the data offload and storage units.
2022-04-28 14:31:32 +03:00
Laszlo Nagy 3bf7b6c80f util_hbm: Initial version
This IP serves as storage interfacing element for external memories like
HBM or DDR4 which have AXI3 or AXI4 data interfaces.

The core leverages the axi_dmac as building blocks by merging an array of
simplex DMA channels into duplex AXI channels. The core will split the
incoming data from the source AXIS interface to multiple AXI channels,
and in the read phase will merge the multiple AXI channels into a single
AXIS destination interface.
The number of duplex channels is set by syntheses parameter and must be
set with the ratio of AXIS and AXI3/4 interface.

Underflow or Overflow conditions are reported back to the data offload
through the control/status interface.

In case multiple AXI channels are used the source and destination AXIS
interfaces widths must match.
2022-04-28 14:31:32 +03:00
David Winter 6be4ea92a7 library: axi_tdd: Make synchronization stage optional
Signed-off-by: David Winter <david.winter@analog.com>
2022-04-20 10:54:53 +03:00
David Winter 73468d662b axi_tdd: Add false paths to tdd sync input
This allows the external synchronization input to be driven from
asynchronous sources like a 1 PPS signal or just signals from different
clock domains in general.

Signed-off-by: David Winter <david.winter@analog.com>
2022-04-20 10:54:53 +03:00
Iulia Moldovan 63089a7c5d library/axi_ad9361/intel: Update I/O format 2022-04-08 11:00:04 +03:00
Iulia Moldovan 7a5ecb592e library/data_offload: Remove empty module data_offload_control 2022-04-07 17:17:47 +03:00
Adrian Costina 18b5fabde0 library: Remove unused IPs 2022-04-06 14:57:37 +03:00
AndrDragomir 60be01f2eb axi_clock_monitor: Fix various issues
- Replace .xdc file
- Remove parameter dependency for wire signals
- Fix typo
- Remove unnecessary comments
- Fix signal width
2022-04-05 12:23:33 +03:00
Iulia Moldovan fe713a5e98 library/axi_dmac: Rename 2d_transfer to dmac_2d_transfer
Update the file according to HDL guideline.
Replace all occurrences of 2d_transfer with dmac_2d_transfer.
Update axi_dmac/Makefile.
2022-04-01 16:02:46 +03:00
Iulia Moldovan d9ec44657f libraries: Correct module name according to the filename 2022-04-01 16:02:46 +03:00
PopPaul2021 0d44bfb4dd
axi_hdmi_tx update for: ZedBoard, ZC706, ZC702, de10nano, ADRV9361-Z7035 (#897) 2022-03-29 16:51:21 +03:00
Adrian Costina de70157e3a xilinx/common:ad_data_out.v: Fix typo 2022-03-29 16:50:20 +03:00
AndrDragomir 204dff3b73 library: Adding axi_clock_monitor ip core 2022-03-29 10:02:42 +03:00
Adrian Costina 31c21cad7f xilinx/common: Add CLKEDGE parameter to ad_data_* module 2022-03-25 15:10:12 +02:00
Nick Pillitteri c1721e18dd account for ADI_VIVADO_IP_LIBRARY global variable when adding subcores 2022-03-24 16:29:49 +02:00
alin724 6a252ec067 util_mii_to_rmii: Fix 100 Mbps configuration functionality 2022-03-22 14:30:24 +02:00
Nick Pillitteri 084d44c978 add ability to customize Xilinx IP library version to value other than "user" from a global variable. 2022-03-17 09:43:39 +02:00
Laszlo Nagy e66c5282bc axi_adrv9001: Expose IODELAY_CTRL parameter to top level 2022-03-02 11:06:12 +02:00
Laszlo Nagy 4c7be950d1 ad_ip_jesd204_tpl_adc: Fix latency of valid signal 2022-02-16 10:27:50 +02:00
Laszlo Nagy f245448976 ad_ip_jesd204_tpl_ : Add missing dependency 2022-02-07 19:14:01 +02:00
Laszlo Nagy b5092662d5 ad_ip_jesd204_tpl_adc: Refactor external sync
- Add EXT_SYNC option
- Gate valid while in reset
2022-02-07 19:14:01 +02:00
Laszlo Nagy 8c7cca4277 common/up_adc_common: Add ext sync regs 2022-02-07 19:14:01 +02:00
Laszlo Nagy 1b06c74919 common/up_dac_common: Add manual sync request 2022-02-07 19:14:01 +02:00
Laszlo Nagy db49aa652f common/up_dac_common: Add support for explicit disarm control 2022-02-07 19:14:01 +02:00
Laszlo Nagy 4e644e4e74 jesd204/ad_ip_jesd204_tpl_dac: External sync refactor
- Expose EXT_SYNC parameter to sw
- Add external manual sync request
- Add rst to interface
2022-02-07 19:14:01 +02:00
Laszlo Nagy 1ca5abc91e common/up_xfer_cntrl: Fix transfer done timing
up_xfer_done should signalize when a previous control set is
transferred to the other clock domain and the current control set is latched.

If a bit from the up_data_cntrl changes, it should stay in that state until
the up_xfer_done asserts.
2022-02-07 19:14:01 +02:00
alin724 170ce42e3e util_mii_to_rmii: Initial commit 2022-02-03 10:23:12 +02:00
AndreiGrozav 38f3627695 ad_dds: Fix DDS start samples
When using a CLK_RATIO > 1 the first n samples(n=CLK_RATIO) after sync, are
noisy. This is because the phase accumulator data is passed to the phase to
amplitude converter, during the phase synchronization step.
2022-01-31 14:07:11 +02:00
Iulia Moldovan b26b4c00f0 ad9783: Clean-up parameters and module instances 2022-01-25 18:24:43 +02:00
Laszlo Nagy 889447e900 axi_ad9361: make IODELAYCTRL insertion optional 2022-01-25 09:50:31 +02:00
Laszlo Nagy bc8e7881f2 axi_dmac: Hook up ID
Signed-off-by: Laszlo Nagy <laszlo.nagy@analog.com>
2022-01-25 09:50:22 +02:00
Iulia Moldovan f3cf7508c8 ad9783: Update Makefile 2022-01-20 12:31:57 +02:00
LIacob106 9d94f21d89 scripts/adi_xilinx_device_info_enc.tcl: Change regex for vcu128
The regex does not match vcu128 as Ultrascale+. It matches for Ultrascale.
2022-01-12 17:32:47 +02:00
Filip Gherman 9d8097389c library/jesd204/jesd204_common/pipeline_stage.v: Initialize pipeline stage register 2022-01-12 13:43:20 +02:00
Filip Gherman 080925e8fe library/jesd204: tpl timing bug fix 2022-01-12 10:14:55 +02:00
Iulia Moldovan 08f029c757 axi_ad9783: Initial commit 2022-01-07 14:04:08 +02:00
David Winter fcd3bfd349 util_pulse_gen: Reload registers when counter is at one
This patch fixes an issue where the pulse width is only updated two
periods after the current one.

Signed-off-by: David Winter <david.winter@analog.com>
2022-01-04 15:02:05 +02:00
AndreiGrozav c2d960e029 axi_adrv9001: Add external sync support
The external sync must be synchronous to the reference clock, in order
to obtain a deterministic synchronization of the interface.
2021-12-16 15:16:30 +02:00
Laszlo Nagy 41525f348b axi_adrv9001/axi_adrv9001_core.v: Disable TDD and IOCTRL if second SSI interface is disabled 2021-12-08 17:31:53 +02:00
Laszlo Nagy dfe153dc68 axi_adrv9001/axi_adrv9001_tdd.v: Add disable option for TDD 2021-12-08 17:31:53 +02:00
Laszlo Nagy 8cc0367e8f axi_adrv9001: Hide disabled interfaces
Signed-off-by: Laszlo Nagy <laszlo.nagy@analog.com>
2021-12-08 17:31:53 +02:00
Laszlo Nagy 6a4b46ebb4 axi_adrv9001: Make Rx2 and Tx2 source synchronous interfaces optional
If the Rx2 and Tx2 SSI are disabled the rx1,tx2 data paths are forced to
R1 mode.

Signed-off-by: Laszlo Nagy <laszlo.nagy@analog.com>
2021-12-08 17:31:53 +02:00
sergiu arpadi c1ca578343 axi_ad7616: Fix sync port 2021-11-22 15:22:16 +02:00
Laszlo Nagy 8e0a45dea9 jesd204_rx/jesd204_lane_latency_monitor.v: Fix for datapath width of 4
Current implementation is correct only for datapath width of 8.
The buswidth of latency measurement inside a beat has a fixed width (3 bits)
for each lane that must be taken in account when computing the total latency.

Signed-off-by: Laszlo Nagy <laszlo.nagy@analog.com>
2021-11-19 18:14:43 +02:00
Laszlo Nagy 7e5a638386 jesd204_versal_gt_adapter_rx/tx: Infer Versal GT interface 2021-11-19 14:01:48 +02:00
Laszlo Nagy b25c37a8cc axi_adrv9001/intel: Add dummy parameters to match Xilinx interface
Signed-off-by: Laszlo Nagy <laszlo.nagy@analog.com>
2021-11-12 14:09:14 +02:00
Laszlo Nagy 36d0a8b3e8 library:util_pad: Initial version
Data to DMA/system memory must be presented in widths of multiple of 8 bits,
however this padding is not optimal if is done in the transport layer
since this will affect the DAC/ADC FIFO or offload storage.

This utility block adds or removes padding from sample stream in case the
sample with is not multiple of 8 bits, and can be placed between the DMA
and FIFO/Offload blocks.
2021-11-10 14:03:34 +02:00
Laszlo Nagy cb8cf4b3d2 jesd204/scripts: Helper procedure for TPL width calculation 2021-11-10 14:03:34 +02:00
Laszlo Nagy 5dd9fd4832 axi_dmac: Allow wider FIFO/AXI Stream interface
On large projects with multiple channels the databus on the FIFO/AXI
stream interface can get wider that 1024 bits.

This commit allows a wider range for all the interfaces,
in case for the memory mapped interfaces where the range is 32-1024 the
user selects a bus width out of range that will be handled by the IPI.
2021-11-10 14:03:34 +02:00