369dad60b0
axi_ad9361: Add Altera SERDES interface support
2016-10-11 17:59:19 +03:00
52194f0fea
axi_ad9361: Add DRP connection to the interface module
2016-10-11 17:59:12 +03:00
7194d2eccc
axi_ad9361: Grup interfaces to add support for more carriers
2016-10-11 17:58:49 +03:00
1b9d2d434c
axi_ad9361_tdd: Delete unused register
2016-10-05 17:41:08 +03:00
43b3761b80
axi_ad9361: Flop the tx and rx valid
2016-10-03 12:24:04 +03:00
b4fac96aad
axi_ad9361- independent disables
2016-09-28 15:45:27 -04:00
f7fb3ccaca
axi_ad9361: Change the data path gating
...
Bring up the datapath gating from the TDD controller module.
2016-09-28 16:36:13 +03:00
1a11e28821
ad9361- dac data path split
2016-09-23 16:13:46 -04:00
7be6168b2e
ad9361- adc data path split
2016-09-23 13:42:14 -04:00
78f7384150
ad9361- vivado synthesis warnings fix
2016-09-22 13:41:18 -04:00
913eafed48
up_drp : Update the DRP interface to support Altera platforms
2016-09-21 15:00:45 +03:00
2159f78c80
axi_ad9361: Delete invalid assignment of a generated wire
2016-09-16 17:38:08 +03:00
a183e51a12
axi_ad9361: Add parameter R1_MODE_EN
...
R1_MODE_EN can disable the second I/Q channel of the core. This way
the user can save resources by cutting down the size of the core.
2016-09-09 16:34:11 +03:00
e42206e510
axi_ad9361: Add a TDD enable/disable parameter
2016-09-09 14:38:28 +03:00
be41a8bcaa
axi_ad9361: Delete debug ports of the tdd module
2016-09-09 14:38:28 +03:00
9799599eee
library/ad9361- add dac clk sel
2016-08-26 10:31:00 -04:00
6a8ca8107a
common: Added common ad_dcfilter stub for altera.
2016-08-16 17:37:16 +03:00
0cd608a7e2
lib_refactoring: Update Make files
2016-08-08 16:38:38 +03:00
aad8c265bc
lib_refactoring: Fix path for CMOS sources
2016-08-08 15:07:54 +03:00
df36902713
lib_refactoring: Fix path of the IO macros
2016-08-08 15:07:19 +03:00
d60bce654c
Makefiles: Updated Makefiles so they run correctly with gnuwin32 tools
2016-08-05 15:16:04 +03:00
58b220ba81
ad_tdd_control: Add an on/off switch to the receive datapath
...
For a more robust control, add an on/off switch to the receive datapath too,
in order to filter out transition noises.
2016-08-01 11:49:27 +03:00
7485d27d37
ad9361/altera- device-family variable
2016-06-14 12:28:13 -04:00
5d437083cc
ad9361/altera- a10+ only
2016-06-14 12:19:54 -04:00
c293c04634
hdl make updates
2016-06-01 13:53:09 -04:00
a262eb7ab3
ad9361- output-rst - associated-rst issue?
2016-05-18 13:24:13 -04:00
d7f0bd1b76
ad9361- add reset sink
2016-05-18 13:24:13 -04:00
bb4ed42a93
ad9361- add missing wires
2016-05-18 13:24:13 -04:00
68329de738
ad9361- interface updates
2016-05-16 12:19:38 -04:00
3871d3ce2b
ad9361-c5/a10 - updates
2016-05-09 13:54:08 -04:00
bdfa383622
library/axi_ad9361: tdd false paths
2016-05-04 13:42:12 -04:00
ef6c99ecab
library/axi_ad9361: hw component updates
2016-05-04 13:42:12 -04:00
3b5e44e37d
library/axi_ad9361: mmcm rst for plls
2016-05-04 13:42:12 -04:00
16a13b2023
library/axi_ad9361: add rst/locked to clock
2016-05-04 13:42:11 -04:00
385ed31a45
make files update
2016-04-29 10:17:35 -04:00
3f5e1e1203
ad9361- dev_if module name change
2016-04-29 10:17:35 -04:00
243d3e6e41
ad9361- a10soc sdc files
2016-04-29 10:17:35 -04:00
aa2aa902bf
ad9361- a10soc updates
2016-04-29 10:17:35 -04:00
f411d29e30
ad9361- a10soc changes
2016-04-29 10:17:35 -04:00
779d014750
ad9361-common alt/xil interface
2016-04-29 10:17:35 -04:00
33b265a742
Makefile: Update Makefiles
2016-03-14 09:31:17 +02:00
583ef82fd0
ad9361- cmos mode
2016-03-04 10:39:48 -05:00
7d2939be92
ad9361- cmos mode initial commit
2016-03-04 10:39:48 -05:00
a747fad540
axi_ad9361: tx_valid must be controlled by the TDD controller
2016-02-12 14:33:34 +02:00
e381d5170c
util_tdd_sync: Update the synchronization interface
...
Simplify the synchronization interface, there is one signal line between the synchronization module and transceiver core.
2016-02-12 14:27:37 +02:00
12c95b059d
ad_tdd_control: Remove tdd_enable_synced control line
...
For a better timing and control, the valid control lines are gated with flops, instead of combinatorial logic.
This is the main reason why we do not need the tdd_enable_synced signal anymore. The out coming data is delayed by one clock cycle to keep data and control lines synced.
2015-12-03 11:16:28 +02:00
275ec3d3a8
axi_ad9361: Updated altera interfaces, added FIFO conduits per channel
2015-11-24 11:21:08 +02:00
250f3c917b
axi_ad9361: Removed old signals from the altera device interface module
2015-11-24 11:20:35 +02:00
fc0f4bc414
axi_ad9361: Delete the old sync generator from the core
...
+ Define two control signal for util_tdd_sync : tdd_sync_en and tdd_terminal_type
+ Delete to old ad_tdd_sync.v instances from the core
+ Update Make files
+ Update ad_tdd_control: add additional CDC logic for tdd_sync (the sync comes from another clock domain)
+ Update the ad_tdd_sync module: it's just a simple pulse generator, the pulse period is defined using a parameter, pulse width is fixed: 128 x clock cycle
+ Update TDD regmap: tdd sync period is no longer software defined
2015-11-11 11:06:19 +02:00
c03983ca54
ad_tdd_sync/control: Update TDD logic
...
+ Redesign the TDD counter FSM
+ Make the sync logic independent from the tdd control
2015-09-25 19:11:23 +03:00
AndreiGrozav
Istvan Csomortani
Rejeesh Kutty
Adrian Costina