Commit Graph

34 Commits (369dad60b0928667b8e0d438591f1a6a46cb95bb)

Author SHA1 Message Date
Shrutika Redkar 52b544bb66 hdl-vivado-2016.2- auto infer bus interfaces 2016-07-28 13:44:57 -04:00
Istvan Csomortani 36febf8591 Merge branch 'master' into dev
Conflicts:
	library/axi_ad9361/axi_ad9361_ip.tcl
	library/axi_dmac/Makefile
	library/axi_dmac/axi_dmac_constr.ttcl
	library/axi_dmac/axi_dmac_ip.tcl
	library/common/ad_tdd_control.v
	projects/daq2/common/daq2_bd.tcl
	projects/fmcjesdadc1/common/fmcjesdadc1_bd.tcl
	projects/fmcomms2/zc706pr/system_project.tcl
	projects/fmcomms2/zc706pr/system_top.v
	projects/usdrx1/common/usdrx1_bd.tcl

This merge was made, to recover any forgotten fixes from master,
before creating the new release branch. All conflicts were reviewed
and resolved.
2015-11-26 13:38:11 +02:00
Lars-Peter Clausen a7f4b11624 axi_dmac: Beautify IPI GUI
Group the axi_dmac parameters by function and provide a human readable name
for the IPI GUI. This makes it easier to understand what parameter does
what when using the IPI GUI to configure the core.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-21 17:58:01 +02:00
Lars-Peter Clausen 5b5a4707d2 axi_dmac: Add validation values to IPI package
Add validation values for the different configuration parameters. This
enables the tools to check whether the configured value is valid and avoids
accidental misconfiguration.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-21 17:58:01 +02:00
Lars-Peter Clausen 12fc6d1672 axi_dmac: Indicate that the core does not issue narrow AXI bursts
The axi_dmac core does not issue narrow AXI bursts. Indicate this by
setting the SUPPORTS_NARROW_BURST property to 0 on both AXI master
interfaces.

This allows connected slaves to know that they will not receive narrow
bursts, which allows them to disable support for it.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-18 15:27:18 +02:00
Lars-Peter Clausen f079b2193a axi_dmac: Add support for auto-detecting asynchronous clock configuration
Add support for querying the clock domains of the clock pins for the
axi_dmac controller. This allows the core to automatically figure out
whether its different parts run in different clock domains or not and setup
the configuration parameters accordingly.

Being able to auto-detect those configuration parameters makes the core
easier to use and also avoids accidental misconfiguration.

It is still possible to automatically overwrite the configuration
parameters by hand if necessary.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-18 15:27:15 +02:00
Lars-Peter Clausen 91bb54467b axi_dmac: Generate per core instance constraint file
When having multiple DMA cores sharing the same constraint file Vivado
seems to apply the constraints from the first core to all the other cores
when re-running synthesis and implementation from within the Vivado GUI.

This causes wrong timing constraints if the DMA cores have different
configurations. To avoid this issue use a TTCL template that generates a
custom constraint file for each DMA core instance.

This also allows us to drop the asynchronous clock detection hack from the
constraint file and move it to the template and only generate the CDC
constraints if the clock domains are asynchronous.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-18 15:27:12 +02:00
Lars-Peter Clausen 5af371db6b axi_dmac: Generate per core instance constraint file
When having multiple DMA cores sharing the same constraint file Vivado
seems to apply the constraints from the first core to all the other cores
when re-running synthesis and implementation from within the Vivado GUI.

This causes wrong timing constraints if the DMA cores have different
configurations. To avoid this issue use a TTCL template that generates a
custom constraint file for each DMA core instance.

This also allows us to drop the asynchronous clock detection hack from the
constraint file and move it to the template and only generate the CDC
constraints if the clock domains are asynchronous.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-15 19:54:33 +02:00
Istvan Csomortani 6acb350ee5 axi_dmac: Update for axi_dmac_constr.xdc
Parameter called 'processing_order' default value is 'late'. No need to specify it at process call.
2015-09-09 12:08:35 +03:00
Lars-Peter Clausen e0b5044aa3 axi_dmac: Disable dummy AXI ports for Xilinx IPI
The memory mapped AXI interfaces for the AXI-DMAC are uni-directional.
Which means they are either write-only or read-only. Unfortunately the
Altera tools can't handle this, so we had to add dummy signals for the
other direction.

The Xilinx tools on the other hand handle uni-directional AXI interfaces
and in fact IPI can do a better job and use less resources when creating
the AXI interconnects when it knows that the interface is uni-directional.
So always disable the dummy ports for the IPI package.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-01 11:29:36 +02:00
Istvan Csomortani da315eb6c0 library: 2015.2 updates
IPI bus interface names have changed in this new release.
2015-08-25 09:13:24 +03:00
Lars-Peter Clausen 0d482e7ef6 axi_dmac: Disable dummy AXI ports for Xilinx IPI
The memory mapped AXI interfaces for the AXI-DMAC are uni-directional.
Which means they are either write-only or read-only. Unfortunately the
Altera tools can't handle this, so we had to add dummy signals for the
other direction.

The Xilinx tools on the other hand handle uni-directional AXI interfaces
and in fact IPI can do a better job and use less resources when creating
the AXI interconnects when it knows that the interface is uni-directional.
So always disable the dummy ports for the IPI package.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-08-20 18:25:01 +02:00
Lars-Peter Clausen 37c14e782d axi_dmac: Disable dummy AXI ports for Xilinx IPI
The memory mapped AXI interfaces for the AXI-DMAC are uni-directional.
Which means they are either write-only or read-only. Unfortunately the
Altera tools can't handle this, so we had to add dummy signals for the
other direction.

The Xilinx tools on the other hand handle uni-directional AXI interfaces
and in fact IPI can do a better job and use less resources when creating
the AXI interconnects when it knows that the interface is uni-directional.
So always disable the dummy ports for the IPI package.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-08-20 18:12:10 +02:00
Istvan Csomortani 0d1d8310fd axi_dmac: Parameter changes
Update parameters on inc_id.h and axi_dmac_ip.tcl
2015-08-20 16:06:26 +03:00
Lars-Peter Clausen c372064302 Add .gitattributes file
Add .gitattributes file which sets up the eol encoding handling. This will
make sure that we get a uniform eol encoding across different operating
systems.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-07-01 18:43:51 +02:00
Lars-Peter Clausen 6862655b0d Add .gitattributes file
Add .gitattributes file which sets up the eol encoding handling. This will
make sure that we get a uniform eol encoding across different operating
systems.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 11:07:10 +02:00
Lars-Peter Clausen f51c941c2d axi_dmac: Set proper constraints
Instead of just marking all clock domains as asynchronous set the
appropriate constraints for each CDC path.

For single-bit synchronizers use set_false_path to not constraint the path
at at all.

For multi-bit synchronizers as used for gray counters use set_max_delay with
the source clock period domain to make sure that the signal skew will not
exceed one clock period. Otherwise one bit might overtake another and the
synchronizer no longer works correctly.

For multi-bit synchronizers implemented with hold registers use
set_max_delay with the target clock period to make sure that the skew does
not get to large, otherwise we might violate setup and hold time.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-15 17:20:26 +02:00
Lars-Peter Clausen f6594e276e Bring back AXIS FIFO as a separate module
Bring back the AXIS FIFO as a separate module instead of embedding it into
the DMAC module. This makes it possible to use it in other modules outside
of the DMAC.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-15 17:20:06 +02:00
Lars-Peter Clausen b6458f9aab axi_dmac: Move axi_repack block to its own module
Move the axi_repack block to its own module. This allows it to use it
outside of the DMA controller.

Also rename it to util_axis_resize to better reflect its function.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-08 15:55:17 +02:00
Lars-Peter Clausen 6ba0667939 axi_dmac: Add fifo_wr/fifo_rd interfaces
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-08 13:29:25 +02:00
Lars-Peter Clausen d17cd22ef1 adi_ip.tcl: Allow to directly specify the vlnv string for adi_add_bus()
Modify the adi_add_bus() function to take the full vlnv strings instead of just the bus type.

This makes the function more flexible and e.g. allows to handle buses from other vendors.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-08 13:29:25 +02:00
Rejeesh Kutty 7224ca1f0c dma: moved 2015-04-07 15:35:47 -04:00
Istvan Csomortani 96899313d8 axi_dmac: Fix constraint
Change the constraint file extension to .xdc, no more need for the .tcl workaround.
2015-01-23 18:51:25 +02:00
Adrian Costina 121a416916 axi_dmac: Fixed constraints for axi_dmac core 2014-10-22 13:07:55 +03:00
Lars-Peter Clausen 22169c4a9c axi_dmac: Add default driver values for optional input ports
This silences warnings from the tools about undriven ports.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-10-10 16:25:46 +03:00
Lars-Peter Clausen e7dbdff60c axi_dmac: Hide fifo_wr_sync signal if C_SYNC_TRANSFER_START != 1
The fifo_wr_sync signal is only used when C_SYNC_TRANSFER_START = 1, so hide it otherwise.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-10-10 16:25:41 +03:00
Lars-Peter Clausen 8557073b56 axi_dmac: Hide fifo_wr bus when source type is not the fifo interface
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-10-10 16:25:33 +03:00
Lars-Peter Clausen 3e6f553ce3 axi_dmac: Add clock signal spec for m_axis/s_axis bus
This silences warnings from the tools about having no clock assigned to the bus.
Also fix the name of the TVALID signal.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-10-10 16:25:24 +03:00
Rejeesh Kutty 88a3b7f8fd library: remove all constraints for now 2014-10-07 16:59:19 -04:00
Lars-Peter Clausen c927e90ee1 axi_dmac/axi_fifo: Add missing file
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-09-15 21:04:57 +02:00
Rejeesh Kutty 1396a215e5 library: local constraints 2014-08-14 15:09:47 -04:00
Rejeesh Kutty 56ddce1e8c dmac: create fifo interface to avoid being treated as axi control stream 2014-05-27 10:25:14 -04:00
Lars-Peter Clausen f02ba999ae axi_dmac: Add support for DMA bus widths other than 64 bit
There were a few place in the core where it assumed a 64-bit wide bus. Make this
configurable using parameters. The patch also adds support for having different
DMA bus widths on the source and destination side.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-03-13 13:20:10 +01:00
Adrian Costina 831c19ea84 Added axi_dmac, axi_fifo and misc files in library 2014-03-06 18:16:02 +02:00