Rename "idle bus" to "bus available" per specification:
* Tune it to require < 1us.
Rename "IBI auto" to "IBI listen":
* Clarify that the controller is listening for IBI's:
* Explain that this field should be set.
* Fix for known IBI's DA with IBI disabled.
Signed-off-by: Jorge Marques <jorge.marques@analog.com>
New features:
1. External sync force the phase align. The external sync was used to align
the phases of enabled pwms, but only after being armed by a
load_config signal toggle.
This feature lets the user decide between using load_config to
arm and wait for a neg-edge of sync or automatic phase align trigger
on the ext_sync neg-edge.
2. Force align. Lets the user chose between immediately stopping the
active pulses and realigning them, or waiting for all running pulse
periods end, before realigning.
3. Start at sync. When this feature is activated, the pulses will start immediately
after the trigger event. Otherwise, each pulse will start after a period
equal to the one for which it is set.
4. Use parameters to set the default status after reset of the
- soft reset
- start at sync
- force align
- ext sync align
Update regmap.
Fixes:
1. The polarity on disabled channels was staying high instead of low.
2. Fix 0 and 100 proc duty cycle configuration.
Signed-off-by: AndreiGrozav <andrei.grozav@analog.com>
Signed-off-by: Alin-Tudor Sferle <Alin-Tudor.Sferle@analog.com>
docs: Add JESD204 documentation in sphinx
Fixes several semantic issues from the original doc in wiki
Implicit path to library when the doc is hierarchically coherent with the
library.
Signed-off-by: Carlos Souza <carlos.souza@analog.com>
Co-authored-by: Jorge Marques <jorge.marques@analog.com>
* SPI Engine: Add registers for Offload memory and FIFO sizes
Adds registers at dword 0x04 and 0x05, respectively allowing software
to get the sizes of the Offload Module memories (command and sdo) or
the sizes of the FIFOs on the AXI regmap.
Signed-off-by: Laez Barbosa <laez.barbosa@analog.com>
Use tcl script instead of static xmls for the interface.
Easier to maintain and are not gitignored.
Rename spi_master to spi_engine because every interface should be
prefixed by the IP name; in this case, spi_engine.
Also, remove interface/*.sv files on make clean and git ignore them.
Signed-off-by: Jorge Marques <jorge.marques@analog.com>
The extensions have been moved to docs tools.
The source code is available at
https://github.com/analogdevicesinc/doctools
And is installed as before:
(cd docs ; pip install -r requirements.txt --upgrade)
Since the package is listed on the requirements.txt file.
Also, add index for library and projects
Signed-off-by: Jorge Marques <jorge.marques@analog.com>
Set validation ranges for DATA_WIDTH and NUM_OF_CS for the expected
min/max values in the verilog source code.
Also, fix swapped description for CPHA in the documentation.
Signed-off-by: Carlos Oliveira <caosjr8@gmail.com>
Replaces Symbolator with custom component diagram generator for more
reliable diagrams.
It uses the IP-XACT file, if it is not found, a placeholder is added
instead.
Signed-off-by: Jorge Marques <jorge.marques@analog.com>
Import aiohttp and asyncio only when needed.
Better warning for unknown signals, params.
Use pattern matching in regmap parsing.
Fixup bundle count.
Add lists clarification to guidelines.
Enforce #1229 rules.
Clean-up Makefile.
Use non-breaking hyphen.
Signed-off-by: Jorge Marques <jorge.marques@analog.com>
* SPI Engine: Add execution delay documentation
Add documentation for the different delays on the command path and
data path, including communication between submodules and instruction
execution overhead.
Signed-off-by: Laez Barbosa <laez.barbosa@analog.com>
* docs: Improve consistency
The following rules have been implemented:
1. Tables/lists should contain only the carriers that we support for
that reference design.
2. Hexadecimal addresses should be written in caps and separated
by an underscore (eg. 0x9C4A_0000).
3. Block diagrams should contain subtitles only if there are at
least two different diagrams.
4. The GPIOs should be listed in descending order and should have
the number of bits specified next to their name.
5. All the source code links references should contain the project
name.
6. The infrastructure documentation, if exists, should be listed
after the IP list.
Recommend storing images like any other artifact: in a hierarchical
manner, without "images" subfolders.
This is intended to avoid dangling artifacts when projects are moved,
renamed, or deleted.
Recommend overwriting the page title with a shorter title in the
toctree, so the navigation bar doesn't overflow or get too cluttered.
Add acostina to CODEOWNERS
Signed-off-by: Jorge Marques <jorge.marques@analog.com>
Drop part role, use generic adi instead for root adi domain links.
For future reference, the snipped used was:
find ./docs/projects -type f -exec sed -i 's/:part:/:adi:/g' {} \;
Drop Containerfile.
Add option to validate links status (e.g. 200, 404), intended mostly for CI
use to check if a page has disappeared from the internet.
Validate links uses coroutines to launch multiple tasks concurrently,
but do it in bundles to avoid being rate limited.
Fixup regmap styling.
Add imoldovan, jmarques, spop, lbarbosa as docs codeowners.
Remove branch field for links to the hdl repo.
Change git role to display full path.
Fixup ZedBoard link label, remove IP List, add SYSID_ROM dokuwiki link
in ad716_sdz project.
Signed-off-by: Jorge Marques <jorge.marques@analog.com>
Jorge Marques
Ionut Podgoreanu
AndreiGrozav
bluncan
PIoandan
Jorge Marques
ladace
Stanca Pop
caosjr
Sergiu Arpadi
LBFFilho
Iulia Moldovan
Alin-Tudor Sferle
laurent-19
caosjr
cristianmihaipopa
StancaPop
Ramon Cristopher Calam