Commit Graph

5 Commits (38037641af3a52bb2e61cadaf95fc9f2cf9c96ef)

Author SHA1 Message Date
Jorge Marques e2ca5a991a
spi_engine: Create interface_ip.tcl (#1251)
Use tcl script instead of static xmls for the interface.
Easier to maintain and are not gitignored.
Rename spi_master to spi_engine because every interface should be
prefixed by the IP name; in this case, spi_engine.
Also, remove interface/*.sv files on make clean and git ignore them.

Signed-off-by: Jorge Marques <jorge.marques@analog.com>
2024-02-28 10:31:46 -03:00
laurentiu_popa cf4d2b5a6f projects/ad4134_fmc: Add FMC pinout descripton
* Added txt description of all FMC pins used/unused
* Updated constraint files with FMC pinout location

Signed-off-by: laurentiu_popa <Laurentiu.Popa@analog.com>
2023-10-19 13:55:30 +03:00
Iulia Moldovan c9a7d4d927 Add copyright and license to .tcl, .ttcl files
Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
2023-07-25 15:22:26 +03:00
laurent-19 2ae09c9808 Check guidelines. Remove redundancies
* Removed empty/commented lines
 * Regenerated Makefiles
 * Removed redundancies adc channels data width
 * Set data width 32-bit: max resolution and CRC header

Signed-off-by: laurent-19 <laurentiu.popa@analog.com>
2023-03-29 15:08:07 +03:00
Stanca Pop ee30c64923 projects/ad4134_fmc: Initial commit add support
* Updated reference design: spi trigger, ODR parameters
  - enabled ext_clk for PWM to use 96 MHz spi clk
  - mofified PWM channels used:
  - ch1: ODR - 850 ns period, 130 ns high time
	 ==> max fODR = 1.18 MHz
  - ch0: trigger - 850 ns period, 30 phase shift
         ==> 10 ns between falling ODR rising DCLK
  - spi offload trigger signal: PWM trigger used
 * Moved mem_interconnect to hp1
 * Added dclkio GPIO
 * Updated bd SPIE hierarchy, see library/spi_engine.tcl

Signed-off-by: laurent-19 <laurentiu.popa@analog.com>
2023-03-29 15:08:07 +03:00