Commit Graph

2076 Commits (386cc74ab4f4b5ca3b4b1b9ba98bf0fecf19c037)

Author SHA1 Message Date
Rejeesh Kutty f587aa42d9 a10gx- tx sync 2015-06-10 14:32:25 -04:00
Rejeesh Kutty 04eb998ff1 axi_jesd_gt: constraints 2015-06-10 14:29:06 -04:00
Rejeesh Kutty e3e4af5c51 daq2/zc706: open ports 2015-06-10 14:25:58 -04:00
Rejeesh Kutty e2f4a4c5cf library: make preset registered for timing paths 2015-06-10 13:41:41 -04:00
Rejeesh Kutty df0eaad1e2 gt: constraints 2015-06-10 11:38:15 -04:00
Adrian Costina 97ab5e0ef7 fmcomms1: Update project to integrate the new util_wfifo 2015-06-10 15:16:17 +03:00
Adrian Costina 3d86f140e5 usdrx1: Removed ILA as the ports from axi_jesd_gt were removed 2015-06-10 10:56:55 +03:00
Adrian Costina d6163bea5e axi_jesd_gt: Fixed constraints 2015-06-10 10:56:22 +03:00
Adrian Costina 5e4f572092 axi_ad9122: Fixed constraints 2015-06-10 10:56:03 +03:00
Adrian Costina 8a1f4bf5f6 ad6676,ad9144,ad9152,ad9234,ad9250,ad9434,ad9467,ad9625,ad652,ad9671,ad9680,ad9739a:Set default driver value for overflow, underflow, gpio_in and dac_sync ports 2015-06-09 14:21:12 +03:00
Istvan Csomortani 1fcdeac054 fmcjesdadc1/common: The new GT module does not have integrated monitor/debug ports 2015-06-09 11:50:55 +03:00
Istvan Csomortani 2330d1e27d daq1/common: The new GT module does not have integrated monitor/debug ports 2015-06-09 11:50:27 +03:00
Rejeesh Kutty 00b8c171b8 a10gx: pll locked to reset controller 2015-06-08 15:00:11 -04:00
Adrian Costina a598e1c614 axi_ad9265: Set default driver value for overflow and underflow ports 2015-06-08 17:50:23 +03:00
Adrian Costina ccf887f0ba axi_ad9643: Set default driver values for overflow, underflow and gpio_in ports 2015-06-08 17:48:41 +03:00
Adrian Costina ded0dd5dbe axi_ad9122: fixed constraints, removed unneded drp reset 2015-06-08 17:45:14 +03:00
Istvan Csomortani 4b08df9ed6 ad9361/tdd: Fix generation of tx_valid_* signals
In FDD mode the tx_valid_* signals are generated inside the axi_ad9361_tx module, in function of
the selected dac data rate. In TDD mode, these signals are gated by the tdd_enable and tdd_tx_dp_en signals.
In other words, the tx_valid_* signals will be valid just when tdd_enable and tdd_tx_dp_en is active.
2015-06-08 16:23:32 +03:00
Istvan Csomortani c926daca3a ad9361/tdd: Fix generation of tx_valid_* signals
In FDD mode the tx_valid_* signals are generated inside the axi_ad9361_tx module, in function of
the selected dac data rate. In TDD mode, these signals are gated by the tdd_enable and tdd_tx_dp_en signals.
In other words, the tx_valid_* signals will be valid just when tdd_enable and tdd_tx_dp_en is active.
2015-06-08 16:22:21 +03:00
Adrian Costina be6d6f627a ad9265: Removed ILA 2015-06-08 15:03:34 +03:00
Adrian Costina 25e56a4d03 arradio: renamed fmcomms2 c5soc to arradio 2015-06-08 11:35:21 +03:00
Rejeesh Kutty dc7064ab95 fmcomms2/vc707 - wfifo changes 2015-06-05 12:44:04 -04:00
Rejeesh Kutty ce60056cd5 wfifo: async reset for cpu side 2015-06-05 12:44:04 -04:00
Rejeesh Kutty ab1f9bed10 wfifo: remove srl from sync registers 2015-06-05 12:44:04 -04:00
Istvan Csomortani 25f1ad73f0 fmcomms2/freqcvt: Update SPI interface I/O 2015-06-05 18:16:14 +03:00
Rejeesh Kutty f1e75963a2 fmcomms2: wfifo+pack changes 2015-06-05 09:20:50 -04:00
Rejeesh Kutty da8915296b pack: ip scripts 2015-06-05 09:20:08 -04:00
Rejeesh Kutty 6338dfd8b7 ad9361: ip defaults & rst output 2015-06-05 09:19:39 -04:00
Rejeesh Kutty cb0324c2b1 wfifo: multi-channel option 2015-06-05 09:19:05 -04:00
Istvan Csomortani b3324b3ef9 Merge branch 'dev' into hdl_2015_r1
Conflicts (all tdd related, all solved):
	library/axi_ad9361/axi_ad9361.v
	library/axi_ad9361/axi_ad9361_tdd.v
	library/common/ad_tdd_control.v
	library/common/up_tdd_cntrl.v
2015-06-05 15:51:03 +03:00
Istvan Csomortani 2e877389b2 ad9361_tdd: Some naming and hierarchical changes 2015-06-04 18:09:49 +03:00
Istvan Csomortani 47469ad375 ad9434/ad9467 : Connect reset signal for AXI streaming interface of the device dma 2015-06-04 18:09:48 +03:00
Istvan Csomortani 3b1ea7e528 axi_ad9361/tdd: Cherry picked commit 598ece4 from hdl_2015_r1 branch
598ece4c8d
2015-06-04 18:09:47 +03:00
Rejeesh Kutty a8a71b4971 alt-tq: common file 2015-06-04 11:00:25 -04:00
Rejeesh Kutty f81d22a17a altera- common timing check 2015-06-04 10:56:32 -04:00
Rejeesh Kutty d111692608 daq2/a10gx- ddr-ref @133 2015-06-04 10:53:16 -04:00
Rejeesh Kutty 886c24f597 tq-alt: added 2015-06-04 10:53:14 -04:00
Rejeesh Kutty 6548bcd71f axi_ip- constraints: add rst path 2015-06-04 10:53:13 -04:00
Rejeesh Kutty e02273781f ad_rst- non lpm version 2015-06-04 10:53:12 -04:00
Lars-Peter Clausen 264dbfed35 common: rfsom: Add constraints for the eth1 rx clock
Add clock rate constraints for the eth1 rx clock, otherwise the tools
assume the RX paths are unconstrained and creates a bitstream which
violates hold times which causes bit errors on the RX path.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-03 17:21:43 +02:00
Rejeesh Kutty 91b0f70972 library: remove drp cntrl 2015-06-02 09:58:57 -04:00
Adrian Costina 2b5abf74d7 util_upack: Show upack_valid only if the channel is activated 2015-06-02 11:36:06 +03:00
Rejeesh Kutty 71b5004b25 projects- drp moved to up-clock domain 2015-06-01 14:57:59 -04:00
Rejeesh Kutty 297e885981 library- drp moved to up-clock domain 2015-06-01 14:52:52 -04:00
Rejeesh Kutty f9ffaf457d projects/daq2- drp moved to up clock 2015-06-01 13:39:26 -04:00
Rejeesh Kutty e7470036bf library- drp moved to up clock 2015-06-01 13:39:26 -04:00
Rejeesh Kutty c6ebab7393 library- drp moved to up clock 2015-06-01 13:39:26 -04:00
Rejeesh Kutty 4a701d3895 a10gx- no-ddr 2015-06-01 11:00:02 -04:00
Rejeesh Kutty aa24c442f5 a10gx- no-ddr 2015-06-01 11:00:01 -04:00
Rejeesh Kutty d7b68c39ef altera- sdc 2015-06-01 10:59:59 -04:00
Rejeesh Kutty 2a0bdbebf2 altera- sdc 2015-06-01 10:59:58 -04:00