Commit Graph

4299 Commits (386febaa7edb518351fbb28663695db600f61b63)

Author SHA1 Message Date
AndreiGrozav 7a3c4ab81f arradio: Changed ADC DMA buswidth connection to the DDR to 128 bits
This fixes the bandwidth issue when data is streamed from the DDR and the system works at 61.44 MSPS
2017-10-04 13:01:14 +01:00
STEVE KRAVATSKY ee01ea3736 daq2/a10gx: Add cfi_flash to qsys
+ Add cfi_flash to qsys
   + Set nios reset vector to cfi_flash
2017-10-04 11:30:29 +01:00
Istvan Csomortani a33f3178c2 adrv9371x/a10soc: For receive paths SYNC_TRANSFER must be enabled 2017-10-04 11:29:09 +01:00
Istvan Csomortani a2ee478027 axi_ad9361: Fix incorrect merge
Fix paramter propegation for DAC_CLK_EDGE_SEL
2017-10-03 10:51:35 +01:00
Istvan Csomortani 0064004d34 axi_dmac: Control s_axis_user/fifo_wr_sync validity
The ports s_axis_user or fifo_wr_sync will be active just
if the SYNC_TRANSFER_START is enabled.
2017-10-03 09:32:14 +01:00
Istvan Csomortani 899b8436ad arradio: Fix the last incorrect merge 2017-10-03 09:15:45 +01:00
Istvan Csomortani 08a31a7d9f axi_dmac: Fix the last incorrect merge 2017-10-03 09:15:45 +01:00
Istvan Csomortani 49293f7a87 axi_ad9361: Fix the last incorrect merge
The last merge broke a couple of source files of this core. This
commit brings all the core to a functional state.
2017-10-03 09:15:23 +01:00
Istvan Csomortani 89bd8b44d4 Merge branch 'dev' into hdl_2017_r1 2017-09-26 07:42:19 +01:00
Istvan Csomortani a386a42642 interface: Update the transceiver interfaces
On commit 6d4430 the signal called sel was removed from the transceiver
interfaces. Update the interface definition script.
2017-09-25 18:02:04 +01:00
AndreiGrozav 256dd87dd2 common/microzed: Enable PS CLK1 = 200MHz 2017-09-25 15:16:58 +03:00
Istvan Csomortani 07f3295638 common/a10soc: Update configuration for emif plddr4 IP 2017-09-25 08:57:26 +01:00
Istvan Csomortani 2926a6aaf9 altera/ad_mem_asym: Delete it, QSYS flow is used 2017-09-25 08:57:26 +01:00
Istvan Csomortani 700ed156ab [axi|avl]_dacfifo: Create a separate bypass module for altera/xilinx 2017-09-25 08:56:40 +01:00
AndreiGrozav 3a47567f9c common/a10gx: Chance SPI frequency from 128KHz to 10 MHz 2017-09-19 18:01:18 +03:00
Lars-Peter Clausen 55daa786fa axi_adcfifo: Add missing constraints
Add missing timing exceptions on paths between the DMA and DDR clock
domains. All these paths are properly synchronized using CDC in the HDL,
but are missing timing exceptions in the XDC file. This can lead to timing
errors when building a design using the axi_adc_fifo.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-09-13 19:52:48 +02:00
Adrian Costina cafa811c74 adrv9379: Change the DMA clock to 250 2017-09-11 16:52:44 +03:00
Rejeesh Kutty 58572d746c arradio/c5soc- rd10102013_979 fix 2017-09-05 12:52:41 -04:00
Lars-Peter Clausen c3aa3e8a9c adrv9371: a10soc: Whitespace cleanup
Remove some extra end-of-line whitespace.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-09-05 13:47:49 +02:00
Rejeesh Kutty 6736aaeca1 arradio- add control/status ports 2017-09-01 14:39:18 -04:00
Rejeesh Kutty bb73e7a40f arradio- add control/status ports 2017-09-01 14:39:18 -04:00
Adrian Costina 6ce4494002 adrv9379: Initial commit 2017-09-01 17:28:04 +03:00
Adrian Costina 9a32240cc5 axi_ad9379: Initial commit 2017-09-01 17:26:37 +03:00
Adrian Costina cb2fd6af73 dm2k: Drive the ADC DMA valid from the trigger extracting core 2017-08-30 18:28:52 +03:00
Adrian Costina 6d5b5b50a5 axi_logic_analyzer: Compensate the 4 word latency of util_var_fifo 2017-08-30 18:17:41 +03:00
Adrian Costina f6288dc0a3 util_extract: Compensate 4 word latency 2017-08-30 18:02:09 +03:00
Adrian Costina 54e96c49ae util_var_fifo: Set fix latency of 4 for all interpolation values 2017-08-30 18:01:06 +03:00
Lars-Peter Clausen 3e96903be7 jesd204_rx: rx_ctrl: Fix typo
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-28 16:11:00 +02:00
Adrian Costina 421b4bed41 axi_ad9963: Moved RX configuration bit SCALECORRECTION_ONLY to bit 9 2017-08-28 15:58:00 +03:00
Rejeesh Kutty 5bc927ff94 adrv9364/ccbox- input rf protection 2017-08-25 13:30:46 -04:00
Rejeesh Kutty dc0a71920c adrv9361/ccbox- sort gpio - accidental multiple drivers 2017-08-25 13:30:46 -04:00
Rejeesh Kutty f19b8c62a1 library- add a timer for quick start 2017-08-25 13:28:05 -04:00
Rejeesh Kutty fd8b524953 adrv9361-ccbox/ccfmc- adl5904/gpio updates 2017-08-25 11:23:56 -04:00
Rejeesh Kutty 4050f5ae58 adrv9361- add adl5904 2017-08-24 15:47:17 -04:00
Lars-Peter Clausen e4988aa131 adrv9371x: altera: Convert to ADI JESD204
Convert the ADRV9371 project for Intel/Altera platforms to the ADI JESD204
framework.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-24 17:55:10 +02:00
Lars-Peter Clausen e4bb2beaf1 altera: adi_jesd204: Export link domain reset
Export the reset signal for the link clock domain. This can be used by
external logic that is in the link clock domain to reset itself.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-24 17:43:12 +02:00
Lars-Peter Clausen 853342b201 altera: adi_jesd204: Disable FPLL phase alignment mode
Enabling the phase alignment mode of the FPLL seems to break manual
re-calibration, which is required when changing the lane rates. The
calibration seems to select the wrong VCO frequency band and the PLL no
longer locks.

Disable phase alignment mode for now, this has a negative effects on
deterministic latency, but it is better than not working at all.

Waiting for feedback from Altera/Intel on how to make manual re-calibration
work in phase alignment mode.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-24 17:43:12 +02:00
Lars-Peter Clausen 72a23eeb71 altera: adi_jesd204: Enable avmm_busy flag in the link FPLL register map
To be able to check the FPLL re-configuration arbitration status from
software enable the avmm_busy flag in the register map.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-24 17:42:44 +02:00
Lars-Peter Clausen dd1b1c89f9 jesd204: jesd204_rx: Don't expose internal states on the status interface
The DEGLITCH state of the RX state machine is a workaround for misbehaving
PHYs. It is an internal state and an implementation detail and it does not
really make sense to report through the status interface.

Rework things so that DEGLITCH state is reported as part of the CGS state
on the external status interface.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-24 17:42:44 +02:00
Lars-Peter Clausen e6aacd2f56 axi_dmac: Better support debug IDs when ID_WIDTH != 3
The current layout of the debug ID register assumes that the ID_WIDTH is 3.
Change things so that the padding 0 width depends on the ID_WIDTH
parameter so that we end up with the same register layout regardless of the
value of ID_WIDTH.

Also split things into two registers, this allows for an ID_WIDTH up to 8
(which should hopefully be enough for all practical applications).

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-24 17:42:20 +02:00
AndreiGrozav d05ed29212 adrv9371x_zcu102: Initial commit 2017-08-22 15:48:03 +03:00
AndreiGrozav c0da4e6192 adrv9371x_kcu105: Initial commit 2017-08-22 15:41:49 +03:00
AndreiGrozav 1d67036305 adrv9371x/common: Remove ila_adc and ila_os_adc 2017-08-22 15:37:59 +03:00
AndreiGrozav 6fa45bb378 adrv9371x/common: Fix axi_ad9371_dacfifo/dac_rst assignamen 2017-08-22 15:37:59 +03:00
AndreiGrozav a64998c3ff adrv9371x: Separate ps7 assignaments from common
Move the assignaments/connections for ps7 from common/adrv9371_bd
to zc706/system_bd
2017-08-22 15:37:59 +03:00
AndreiGrozav b7ce81686a common/zcu102: Fix ps8 ref clock 0 frequency assignament 2017-08-22 15:37:59 +03:00
AndreiGrozav 41e247d426 common/zcu102: Add gpio_t connections 2017-08-22 15:37:59 +03:00
Istvan Csomortani deefb33490 avl_dacfifo: Update IP to qsys flow 2017-08-22 09:16:21 +01:00
Istvan Csomortani 7fa8498b3a adrv9371x: DAC_FIFO should get the dma_rst from sys_dma_rstgen 2017-08-22 09:16:21 +01:00
Istvan Csomortani b2550b7aa0 axi_dacfifo: Update constraints 2017-08-22 09:16:21 +01:00