Rejeesh Kutty
|
ff646b0cfc
|
common/a5soc- alt 16.1 updates
|
2017-06-13 09:54:01 -04:00 |
|
Rejeesh Kutty
|
0eacde9158
|
fmcjesdadc1/a5soc- alt 16.1 updates
|
2017-06-13 09:54:01 -04:00 |
Adrian Costina
|
2fc5d08c0b
|
axi_gpreg: Fixed constraints
|
2017-06-13 14:04:43 +03:00 |
|
Rejeesh Kutty
|
6decba3c3b
|
hdlmake.pl updates
|
2017-06-09 16:23:17 -04:00 |
|
Rejeesh Kutty
|
173837f5b2
|
altera- altera ip interfaces has no consistency
|
2017-06-09 16:21:44 -04:00 |
|
Rejeesh Kutty
|
74f9a99655
|
fmcjesdadc1/a5gt- altera 16.1 updates
|
2017-06-09 16:20:49 -04:00 |
|
Rejeesh Kutty
|
2e17e67627
|
common/a5gt- altera 16.1 updates
|
2017-06-09 16:20:15 -04:00 |
|
Rejeesh Kutty
|
688758e6c6
|
scripts/adi_project_alt- add a5soc, a5gt
|
2017-06-09 16:19:29 -04:00 |
|
Rejeesh Kutty
|
227bd3edfe
|
alt_ifconv-- qsys workaround
|
2017-06-09 16:17:34 -04:00 |
|
Rejeesh Kutty
|
ca536d50ac
|
altera 16.1 c5soc updates
|
2017-06-08 15:03:03 -04:00 |
|
Rejeesh Kutty
|
f3af192f30
|
altera 16.1 arradio updates
|
2017-06-08 15:02:46 -04:00 |
|
Rejeesh Kutty
|
ca20309166
|
adi_project_alt: add c5soc
|
2017-06-08 15:02:24 -04:00 |
|
Rejeesh Kutty
|
034aa7c1ee
|
altera 16.1- recommends using fpll for dedicated low skew clock routing
|
2017-06-08 10:50:52 -04:00 |
|
Adrian Costina
|
3f2c885189
|
axi_logic_analyzer: Update triggering delay mechanism
|
2017-06-08 12:01:49 +03:00 |
|
Adrian Costina
|
256a685004
|
axi_adc_trigger: Update triggering delay mechanism
|
2017-06-08 12:00:27 +03:00 |
|
Rejeesh Kutty
|
b8a75a7285
|
hdlmake.pl - updates
|
2017-06-07 10:23:20 -04:00 |
|
Rejeesh Kutty
|
6100a697e8
|
daq3/a10gx- alt 16.1 updates
|
2017-06-07 10:23:20 -04:00 |
|
Rejeesh Kutty
|
40bfd0380e
|
adrv9371x/a10gx- alt 16.1 updates
|
2017-06-07 09:19:14 -04:00 |
Istvan Csomortani
|
83747ddb33
|
ad77681evb: Fix IO constraints
|
2017-06-07 14:28:39 +03:00 |
|
Istvan Csomortani
|
7554887982
|
avl_dacfifo: Fix timing violation
+ Transfer avl_last_beats into dac clock domain
+ Update constraint file
|
2017-06-07 11:02:44 +01:00 |
|
Adrian Costina
|
b7ca17f02b
|
scripts: Change adi_project_create to adi_project_xilinx for creating xilinx projects
|
2017-06-07 12:06:50 +03:00 |
|
Rejeesh Kutty
|
d1bab7ddb9
|
hdlmake.pl- updates
|
2017-06-06 16:10:05 -04:00 |
|
Rejeesh Kutty
|
3f92381bd0
|
daq2/a10gx- project/constraint updates
|
2017-06-06 16:09:15 -04:00 |
|
Rejeesh Kutty
|
dd48929327
|
hdlmake.pl - updates
|
2017-06-06 12:25:35 -04:00 |
|
Rejeesh Kutty
|
5176e427a1
|
common/a10soc- add project create tcl procedure
|
2017-06-06 12:24:13 -04:00 |
|
Rejeesh Kutty
|
f278b6e6c9
|
adrv9371x/a10soc- constraints/project updates
|
2017-06-06 12:23:26 -04:00 |
|
Rejeesh Kutty
|
e34057c2b2
|
adrv9371x/a10gx- constraints/project updates
|
2017-06-06 12:22:31 -04:00 |
|
Rejeesh Kutty
|
e9c49f667f
|
altera- 16.1.2 & a10soc
|
2017-06-06 12:20:44 -04:00 |
|
Rejeesh Kutty
|
41d305b6b6
|
up_clock_mon- name changes
|
2017-06-06 11:36:18 -04:00 |
AndreiGrozav
|
4cc5052b3a
|
util_fir_int: Fix valid assignment
|
2017-06-06 17:53:41 +03:00 |
|
Adrian Costina
|
578ccaaa44
|
adrv9371x:a10gx, update create project command and Makefile
|
2017-06-06 17:30:12 +03:00 |
|
Adrian Costina
|
54a53c015a
|
scripts: changed adi_project_create command to adi_project_altera
|
2017-06-06 17:29:12 +03:00 |
|
Adrian Costina
|
0d99aa02e1
|
m2k: Updated project to work with the fifo_depth related changes
|
2017-06-06 15:37:23 +03:00 |
|
Adrian Costina
|
ac55e850a9
|
axi_logic_analyzer: Added trigger delay register, renamed fifo depth register
|
2017-06-06 15:37:00 +03:00 |
|
Adrian Costina
|
3148c85f73
|
axi_adc_trigger: Added trigger delay register, renamed fifo depth register
|
2017-06-06 15:35:59 +03:00 |
|
Istvan Csomortani
|
491602d88b
|
make: Update make files
|
2017-06-06 12:00:40 +03:00 |
|
Rejeesh Kutty
|
6df97a61ae
|
adrv9364z7020- fix enable/en_agc mixup
|
2017-06-05 16:06:27 -04:00 |
|
Rejeesh Kutty
|
eadbf9ae30
|
altera- remove default assignments from procedure
|
2017-06-05 15:25:38 -04:00 |
|
Rejeesh Kutty
|
0bd22e78d9
|
altera- adi-project-create version
|
2017-06-05 15:24:35 -04:00 |
|
Rejeesh Kutty
|
1b1c7ffa61
|
adi_project- altera version
|
2017-06-05 15:13:21 -04:00 |
|
Rejeesh Kutty
|
95c446a41d
|
adi_ip- initialize xdc list when ip is created
|
2017-06-01 15:49:18 -04:00 |
|
Rejeesh Kutty
|
6a437472f2
|
jesd204-sub-ip- no top files
|
2017-06-01 15:48:48 -04:00 |
|
Istvan Csomortani
|
50cdb6db67
|
Merge branch 'jesd204' into dev
|
2017-05-31 20:44:32 +03:00 |
|
Istvan Csomortani
|
cb4e8f66ef
|
axi_ad9963: Delete unused source from *_ip.tcl
|
2017-05-31 18:27:47 +03:00 |
|
Istvan Csomortani
|
84b2ad51e2
|
license: Add some clarification to the header license
|
2017-05-31 18:18:56 +03:00 |
|
Istvan Csomortani
|
b6d5dbf1fc
|
license: GPL must be GPL v2
|
2017-05-31 18:18:45 +03:00 |
|
Adrian Costina
|
3a4a91b6f1
|
util_extract: Estetic changes
|
2017-05-31 11:27:32 +03:00 |
|
Rejeesh Kutty
|
2d56141bbd
|
altera- 2017-r1 16.1.2
|
2017-05-30 12:21:27 -04:00 |
|
Adrian Costina
|
7aa1673238
|
util_extract: Update parameter names
|
2017-05-29 16:04:56 +03:00 |
|
Istvan Csomortani
|
9bb50f9e74
|
license: Add few cosmetic changes to LICENSE
|
2017-05-29 12:09:43 +03:00 |