Commit Graph

6 Commits (39b2a2b8bb4252d314290533a3437645ce59186f)

Author SHA1 Message Date
Iulia Moldovan 28c06d505f Add/edit copyright and license for .v, .sv files
Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
2023-07-11 15:17:41 +03:00
Iulia Moldovan a88215abc1 axi_adrv9001/intel: Add dummy parameter IODELAY_ENABLE in adrv9001_rx
- Issue introduced by commit 173f4a83d4
 - When IODELAY_ENABLE was inserted in axi_adrv9001_if for adrv9001_rx (Xilinx instance),
   for Intel instance (intel/adrv9001_rx.v) was omitted and caused a build error for
   adrv9001/a10soc

Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
2023-01-18 14:52:30 +02:00
Iulia Moldovan 0c0617d49e libraries: Update modules according to guideline
* Added header license for the files that didn't have
* Modified parentheses
* Removed extra spaces at the end of lines
* Fixed parameters list to be each parameter on its line
* Deleted lines after endmodule and consecutive empty lines
* Fixed indentation

Signed-off-by: Iulia Moldovan <iulia.moldovan@analog.com>
2022-06-28 18:06:56 +03:00
Laszlo Nagy b25c37a8cc axi_adrv9001/intel: Add dummy parameters to match Xilinx interface
Signed-off-by: Laszlo Nagy <laszlo.nagy@analog.com>
2021-11-12 14:09:14 +02:00
Laszlo Nagy 08b0d19731 axi_adrv9001: Populate correct ratio of the SSI interface and user interface clocks
Depending on FPGA technology the physical layer uses different
deserialization factors and corresponding clock division factors to
divide the source synchronous interface clock. This must be
exposed to software so it can act on it while setting the DDS rate.

Xilinx CMOS clock ratio - 4
Xilinx LVDS clock ratio - 4
Intel  CMOS clock ratio - 1
2021-05-26 15:44:45 +03:00
Laszlo Nagy 64f6762a05 library:axi_adrv9001: Initial version
ADRV9001 interfacing IP supports the following modes on Xilinx devices:

A              B  C       D       E       F      G        H
CSSI__1-lane   1  32      80      80      2.5    SDR      8
CSSI__1-lane   1  32      160     80      5      DDR      4
CSSI__4-lane   4  8       80      80      10     SDR      2
CSSI__4-lane   4  8       160     80      20     DDR      1
LSSI__1-lane   1  32      983.04  491.52  30.72  DDR      4
LSSI__2-lane   2  16      983.04  491.52  61.44  DDR      2

Columns description:
A - SSI Modes
B - Data Lanes Per Channel
C - Serialization factor Per data lane
D - Max data lane rate(MHz)
E - Max Clock rate (MHz)
F - Max Sample Rate for I/Q (MHz)
G - Data Type
H - DDS Rate

CSSI - CMOS Source Synchronous Interface
LSSI - LVDS Source Synchronous Interface

Intel devices supports only CSSI modes.
2020-08-24 17:49:12 +03:00