c9a7d4d927
Add copyright and license to .tcl, .ttcl files
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Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
2023-07-25 15:22:26 +03:00
28c06d505f
Add/edit copyright and license for .v, .sv files
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Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
2023-07-11 15:17:41 +03:00
db94628cc6
library & projects: Update Makefiles
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Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
2023-01-27 11:54:05 +02:00
482f0489a3
scripts: Merge adi_env.tcl into a single file
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Move the new adi_env.tcl file from hdl/projects/scripts into hdl/scrips
2022-08-08 13:52:54 +03:00
0c0617d49e
libraries: Update modules according to guideline
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* Added header license for the files that didn't have
* Modified parentheses
* Removed extra spaces at the end of lines
* Fixed parameters list to be each parameter on its line
* Deleted lines after endmodule and consecutive empty lines
* Fixed indentation
Signed-off-by: Iulia Moldovan <iulia.moldovan@analog.com>
2022-06-28 18:06:56 +03:00
591a23156b
Makefiles: Update header with the appropriate license
2021-09-16 16:50:53 +03:00
4a772265a9
Update Quartus Prime version from 19.3.0 to 20.1.0
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adi_project_intel.tcl: Change quartus version to 20.1.0.
library: Set qsys version so that IP instances won't require a specific version.
2021-03-08 11:29:33 +02:00
37254358dd
makefile: Regenerate make files
2020-10-20 12:51:10 +03:00
4a28a4e856
sysid_intel: Added hw.tcl for sysid IP cores
2020-09-11 15:46:06 +03:00
24b5de4438
sysid: Specified clock interface for input clk
2019-11-20 10:43:54 +02:00
4fe5f007cb
system_id: added axi_sysid ip core and tcl
2019-08-06 16:53:11 +03:00
Iulia Moldovan
Iacob_Liviu
Adrian Costina
stefan.raus
Istvan Csomortani
Arpadi