Commit Graph

9 Commits (39c1c83d002cdee7dd506a6633172db5166f84a4)

Author SHA1 Message Date
Rejeesh Kutty 3427965cd2 adxcvr- add u-gth bufg 2016-08-11 10:00:41 -04:00
Shrutika Redkar 829e4155ca modified transceiver configuration files 2016-08-10 14:59:38 -04:00
Istvan Csomortani 1d33d7d7ee lib_refactoring: Move the CMOS interface modules to ~/library/xilinx/common 2016-08-08 15:07:42 +03:00
Istvan Csomortani b806fa3b42 lib_refactoring: Move all the Xilinx common modules to library/xilinx/common 2016-08-08 15:06:10 +03:00
Adrian Costina 5faf4c4976 cleanup: Don't need Makefiles specific to xilinx/altera libraries. Top Makefile covers them 2016-08-05 16:27:52 +03:00
Adrian Costina d60bce654c Makefiles: Updated Makefiles so they run correctly with gnuwin32 tools 2016-08-05 15:16:04 +03:00
Rejeesh Kutty cb23ba8bb7 make- script needs update 2016-08-04 14:17:04 -04:00
Rejeesh Kutty e42b4ea378 hdlmake- updates 2016-08-04 13:28:25 -04:00
Rejeesh Kutty 2b7c976be5 xcvr- altera/xilinx split 2016-08-04 13:26:10 -04:00