Adrian Costina
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591a23156b
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Makefiles: Update header with the appropriate license
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2021-09-16 16:50:53 +03:00 |
Laszlo Nagy
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d9bc014c98
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adrv9001/zcu102: Enable independent Tx from Rx in CMOS mode
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2021-05-26 15:44:45 +03:00 |
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Laszlo Nagy
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677c154134
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adrv9001/zcu102/cmos: Loosen up clock skew constraints to match LVDS settings
Set the same inter clock skew characteristics as used in LVDS mode. The
physical lanes/routes are common on both modes.
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2021-03-04 11:13:10 +02:00 |
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Laszlo Nagy
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dd4c8d6807
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adrv9001/zcu102: Add debug header
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2021-01-26 15:22:41 +02:00 |
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Laszlo Nagy
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728904af09
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adrv9001/zcu102: Run postRoutePhysOpt to close Rx1 to Rx2 path timing
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2021-01-26 15:22:41 +02:00 |
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Laszlo Nagy
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3918d43cd1
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adrv9001/zcu102: Add TDD sync to PMOD0 J55.1
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2021-01-20 13:00:01 +02:00 |
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Laszlo Nagy
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0c2745361b
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adrv9001/zcu102: Add TDD support
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2021-01-20 13:00:01 +02:00 |
Sergiu Arpadi
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6f2f2b8626
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makefile: Regenerate make files
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2021-01-20 01:02:56 +02:00 |
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sergiu arpadi
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acbbd4636a
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sysid: Upgrade framework, header/ip are now at 2/1.1.a
Unify tcl scripts; rename adi_pd_intel.tcl to adi_pd.tcl
add git branch to internal use area; update log prints;
update xilixn projects; fix cn0506 sysid script;
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2021-01-20 01:02:56 +02:00 |
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Adrian Costina
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9093a8c428
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library: Move ad_iobuf to the common library, as it's not Xilinx specific
Updated all system_project and Makefiles
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2020-11-02 16:13:35 +02:00 |
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Laszlo Nagy
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24090fafd8
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adrv9001/zcu102: Loopback VADJ error to the FMC board
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2020-08-31 14:14:03 +03:00 |
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Laszlo Nagy
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72f916fcf5
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adrv9001/zcu102: Update interface signal names based on direction
Let the names of signals from source synchronous interface match the
direction of the signals.
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2020-08-28 13:23:00 +03:00 |
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Laszlo Nagy
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b27f3ac18f
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adrv9001:zcu102: Initial version
Generic project that supports CMOS or LVDS interface for the ADRV9001 transceiver.
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2020-08-24 17:49:12 +03:00 |