Adrian Costina
8ebc8fe4e2
updated makefiles
2016-12-09 23:06:41 +02:00
Rejeesh Kutty
bb9cb86f34
adc/dac- fifo constraints
2016-08-11 10:00:41 -04:00
Adrian Costina
d60bce654c
Makefiles: Updated Makefiles so they run correctly with gnuwin32 tools
2016-08-05 15:16:04 +03:00
Rejeesh Kutty
c293c04634
hdl make updates
2016-06-01 13:53:09 -04:00
Rejeesh Kutty
385ed31a45
make files update
2016-04-29 10:17:35 -04:00
Istvan Csomortani
69d721526a
util_dacfifo: Add constraints file
2016-04-12 13:21:50 +03:00
Istvan Csomortani
255b0ebd40
util_dacfifo: Add dac_xfer_out control
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The dac_xfer_out control signal is asserted while the DAC reads back data. Should be connected to upack/dma_xfer_in.
2016-03-29 16:50:00 +03:00
Istvan Csomortani
373481360b
util_dacfifo: Add a bypass option to the FIFO
2016-03-21 14:14:43 +02:00
Istvan Csomortani
8321d5a4fb
util_dacfifo: Update read out method
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Update the way how the fifo push out its content. By default the fifo pushes out all its content, if an xfer_last signal is received, the fifo saves the last write address, and reads out until the saved address.
2015-10-08 17:13:12 +03:00
Istvan Csomortani
884973fdbb
util_dacfifo: Cosmetic changes
2015-09-25 17:41:44 +03:00
Rejeesh Kutty
c56b534ec0
dacfifo- remove interfaces
2015-08-27 11:18:00 -04:00
Istvan Csomortani
57cfb7cfb1
hdl/library: Update the IP parameters
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The following IP parameters were renamed:
PCORE_ID --> ID
PCORE_DEVTYPE --> DEVICE_TYPE
PCORE_IODELAY_GROUP --> IO_DELAY_GROUP
CH_DW --> CHANNEL_DATA_WIDTH
CH_CNT --> NUM_OF_CHANNELS
PCORE_BUFTYPE --> DEVICE_TYPE
PCORE_ADC_DP_DISABLE --> ADC_DATAPATH_DISABLE
CHID --> CHANNEL_ID
PCORE_DEVICE_TYPE --> DEVICE_TYPE
PCORE_MMCM_BUFIO_N --> MMCM_BUFIO_N
PCORE_SERDES_DDR_N --> SERDES_DDR_N
PCORE_DAC_DP_DISABLE --> DAC_DATAPATH_DISABLE
DP_DISABLE --> DATAPATH_DISABLE
PCORE_DAC_IODELAY_ENABLE --> DAC_IODELAY_ENABLE
C_BIG_ENDIAN --> BIG_ENDIAN
C_M_DATA_WIDTH --> MASTER_DATA_WIDTH
C_S_DATA_WIDTH --> SLAVE_DATA_WIDTH
NUM_CHANNELS --> NUM_OF_CHANNELS
CHANNELS --> NUM_OF_CHANNELS
PCORE_4L_2L_N -->QUAD_OR_DUAL_N
C_ADDRESS_WIDTH --> ADDRESS_WIDTH
C_DATA_WIDTH --> DATA_WIDTH
C_CLKS_ASYNC --> CLKS_ASYNC
PCORE_QUAD_DUAL_N --> QUAD_DUAL_N
NUM_CS --> NUM_OF_CS
PCORE_DAC_CHANNEL_ID --> DAC_CHANNEL_ID
PCORE_ADC_CHANNEL_ID --> ADC_CHANNEL_ID
PCORE_CLK0_DIV --> CLK0_DIV
PCORE_CLK1_DIV --> CLK1_DIV
PCORE_CLKIN_PERIOD --> CLKIN_PERIOD
PCORE_VCO_DIV --> VCO_DIV
PCORE_Cr_Cb_N --> CR_CB_N
PCORE_VCO_MUL --> VCO_MUL
PCORE_EMBEDDED_SYNC --> EMBEDDED_SYNC
PCORE_AXI_ID_WIDTH --> AXI_ID_WIDTH
PCORE_ADDR_WIDTH --> ADDRESS_WIDTH
DADATA_WIDTH --> DATA_WIDTH
NUM_OF_NUM_OF_CHANNEL --> NUM_OF_CHANNELS
DEBOUNCER_LEN --> DEBOUNCER_LENGTH
ADDR_WIDTH --> ADDRESS_WIDTH
C_S_AXIS_REGISTERED --> S_AXIS_REGISTERED
Cr_Cb_N --> CR_CB_N
ADDATA_WIDTH --> ADC_DATA_WIDTH
BUFTYPE --> DEVICE_TYPE
NUM_BITS --> NUM_OF_BITS
WIDTH_A --> A_DATA_WIDTH
WIDTH_B --> B_DATA_WIDTH
CH_OCNT --> NUM_OF_CHANNELS_O
M_CNT --> NUM_OF_CHANNELS_M
P_CNT --> NUM_OF_CHANNELS_P
CH_ICNT --> NUM_OF_CHANNELS_I
CH_MCNT --> NUM_OF_CHANNELS_M
4L_2L_N --> QUAD_OR_DUAL_N
SPI_CLK_ASYNC --> ASYNC_SPI_CLK
MMCM_BUFIO_N --> MMCM_OR_BUFIO_N
SERDES_DDR_N --> SERDES_OR_DDR_N
CLK_ASYNC --> ASYNC_CLK
CLKS_ASYNC --> ASYNC_CLK
SERDES --> SERDES_OR_DDR_N
GTH_GTX_N --> GTH_OR_GTX_N
IF_TYPE --> DDR_OR_SDR_N
PARALLEL_WIDTH --> DATA_WIDTH
ADD_SUB --> ADD_OR_SUB_N
A_WIDTH --> A_DATA_WIDTH
CONST_VALUE --> B_DATA_VALUE
IO_BASEADDR --> BASE_ADDRESS
IO_WIDTH --> DATA_WIDTH
QUAD_DUAL_N --> QUAD_OR_DUAL_N
AXI_ADDRLIMIT --> AXI_ADDRESS_LIMIT
ADDRESS_A_DATA_WIDTH --> A_ADDRESS_WIDTH
ADDRESS_B_DATA_WIDTH --> B_ADDRESS_WIDTH
MODE_OF_ENABLE --> CONTROL_TYPE
CONTROL_TYPE --> LEVEL_OR_PULSE_N
IQSEL --> Q_OR_I_N
MMCM --> MMCM_OR_BUFR_N
2015-08-19 14:11:47 +03:00
Istvan Csomortani
9934cce5d2
util_dacfifo: Add CDC logic for dma_lastaddr register.
2015-05-11 12:20:46 +03:00
Istvan Csomortani
a7c96fdac8
util_dacfifo: General clean up of the IO, input/output data has the same width
2015-05-06 16:32:44 +03:00
Istvan Csomortani
9fba4cb2ef
util_dacfifo: Add support for Slave AXI stream interface.
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The FIFO can be initialized through an AXI stream interface too.
2015-04-27 10:40:55 +03:00
Istvan Csomortani
a100ecd308
util_dacfifo: Update BRAM DAC Fifo
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The fifo will be placed between the DMAC and the Upack module, all the interfaces were updated.
2015-04-21 15:45:56 +03:00
Adrian Costina
dc2b37bd0c
Makefile: Added top level Makefile. Modified behavior of clean and clean-all
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Clean ran for a project will clean only the project files.
Clean-all ran for a project will clean also the library files on which the project depends.
The clean commands will only remove specific files and directories.
The top Makefile allows several options(per suggestion from jameyhicks):
make fmcomms1.zed will run "make all" in projects/fmcomms1/zed/
make clean will run "make clean" for all the projects
make clean-all will run "make clean" for all the projects and libraries
make lib will run "make all" for the library files
2015-04-17 17:22:38 +03:00
Adrian Costina
374f82e7de
makefiles: The clean command for library won't remove the xml files, except for component.xml.
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Updated also the dmac dependencies
2015-04-16 11:53:27 +03:00
Istvan Csomortani
b7d8e38c94
util_dacfifo: General update
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+ Clean out the code, delete unnecessary flops
+ Add support for channel count (C_CH_CNT)
+ FIFO write (data from DMAC/upack) : valid just when xfer_req is asserted, address is free running, new xfer_req resets the address
+ FIFO read (data to DAC) : free running, reads to max address
2015-04-09 11:43:37 +03:00
Rejeesh Kutty
5f8e9a74ea
makefile: updated
2015-04-07 16:32:01 -04:00
Rejeesh Kutty
056d6bbf40
dacfifo: added
2015-04-07 15:55:29 -04:00