1fff1076b1
daq2/a10gx- ethernet fix
2015-09-02 14:31:15 -04:00
01c0fdc809
daq2/a10gx- ethernet fix
2015-09-02 14:31:15 -04:00
1ecd615f92
common/mitx045 : Fix the vdma interface of axi_hdmi_core
2015-09-02 16:33:30 +03:00
9fb336e464
usdrx1: Add DDR FIFO
...
The converters on the usdrx1 generate 2.5GB/s. This more than we can
transport over the HP interconnects to the system memory.
Add a dedicated DDR FIFO to design which can be used to buffer the data
before it is transferred to the main memory.
Also increase the interconnect clock rate from 100MHz to 200MHz and the DMA
FIFO size from 4 to 8, so we can transfer the captured data faster to the
main memory.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-01 11:29:36 +02:00
bbada6ed8f
usdrx1: Add overflow flag to ILA
...
It's useful to know if and when a overflow happens.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-01 11:29:36 +02:00
c67aecc1eb
usdrx1: Disable SYNC_TRANSFER_START for the DMA
...
There is no sync signal in this design, so the flag needs to be set to 0.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-01 11:29:36 +02:00
9b37d6bfe7
pzslb- updates - wip
2015-08-31 15:41:29 -04:00
49430dc2b0
pzslb- copy
2015-08-31 15:41:27 -04:00
879a75a690
pzslb- copy
2015-08-31 15:41:26 -04:00
fdc3dbb805
pzslb- copy
2015-08-31 15:41:25 -04:00
fc79af6edc
pzslb- common
2015-08-31 15:41:24 -04:00
f005de9ee2
pzslb- added
2015-08-31 15:41:23 -04:00
a67ae238f8
rfsom-ps7- ddr settings
2015-08-31 15:39:45 -04:00
212235189f
hdmi-tx- signal name changes
2015-08-28 13:48:33 -04:00
0e20277bc1
hdmi-tx- signal name changes
2015-08-28 13:48:33 -04:00
93fe70790d
hdmi-tx- signal name changes
2015-08-28 13:48:33 -04:00
810fced1ec
hdmi-tx- signal name changes
2015-08-28 13:48:33 -04:00
01852a14de
hdmi-tx- signal name changes
2015-08-28 13:48:33 -04:00
7a1df720e2
rfsom- tdd ensm io changes
2015-08-27 16:26:18 -04:00
6e90ba24e4
rfsom- add rgmii iodelay constraints
2015-08-27 16:26:17 -04:00
15be942b74
daq2-a10gx- ignore cpu2ddr-io paths
2015-08-27 13:54:05 -04:00
a92e049e8f
fmcomms2_bd- another attempt at ila width
2015-08-27 13:17:08 -04:00
90e4cadf4b
daq2/kcu105- xcvr pin loc
2015-08-27 12:40:44 -04:00
b8f9b7040d
fmcomms2- tdd ila fixes
2015-08-27 11:55:41 -04:00
026fad8853
fmcomm2- enable/txnrx- through devif
2015-08-27 11:41:58 -04:00
6a9790484f
fmcomm2- enable/txnrx- through devif
2015-08-27 11:41:56 -04:00
3953ab5e22
rfsom- rgmii upgrade
2015-08-27 11:41:55 -04:00
7c8e56cb09
daq2/kcu105- pin loc is now all errors
2015-08-27 11:18:00 -04:00
89c7a4de79
daq2/kcu105- parameter changes
2015-08-27 11:18:00 -04:00
58fa29b673
daq2- jesd core upgrade
2015-08-27 11:18:00 -04:00
2e1e0939ce
fmcomms2- dma parameters & ila cores upgrade
2015-08-26 14:12:57 -04:00
74a6e33f2d
kcu105: 2015.2.1 updates
2015-08-25 09:12:36 -04:00
4eb28592c8
kcu105: 2015.2.1 updates
2015-08-25 09:12:32 -04:00
971e3395e7
projects/scripts: Update board part names.
...
Property 'board' is deprecated for object type 'project', 'board_part' is used. Update the 'board_part' property names for all Xilinx development boards.
2015-08-25 10:19:57 +03:00
77e2eb7364
projects/common: Fix parameter name for xilinx core axi_gpio
...
Parameter C_GPDATA_WIDTH is changed to C_GPIO_WIDTH.
2015-08-25 10:07:11 +03:00
d3e090da3d
projects/common: Upgrade Xilinx's IP cores
...
To update the projects to Vivado 2015.2 the following IP cores were upgraded:
+ microblaze 9.4 to microblaze 9.5
+ axi_ethernet 6.2 to 7.0
+ mig 6.1 to 7.0
2015-08-25 10:03:49 +03:00
203d7cb470
projects/common: Cosmetic changes.
2015-08-25 09:58:32 +03:00
f08305c979
adv7511_ac701: Fix axi_ethernet core's port connections
2015-08-25 09:54:19 +03:00
af8a48d90e
projects: Fix broken parameters at the common block designs.
...
Fix parameter names for axi_spdif_tx and axi_i2s_adi core instantiations.
2015-08-25 09:25:24 +03:00
78cf0fce0e
ddr/eth- pll refclock is defined by the cores
2015-08-21 14:42:15 -04:00
827fc1e29a
remove auto-pack disable
2015-08-20 13:54:16 -04:00
9e5e7d6805
remove rfsom from fmcomms2
2015-08-20 10:33:43 -04:00
168bcecc31
pzsdr- added
2015-08-20 10:32:48 -04:00
2dabf98089
parameter changes
2015-08-20 08:54:13 -04:00
0dfb3e2019
tcl_scripts: Update Vivado version number to 2015.2.1
2015-08-20 10:50:52 +03:00
d52308f074
axi_dmac: Change parameter name 2D_TRANSFER
...
Parameter name can't start with numbers, 2D_TRANSFER was changed to DMA_2D_TRANSFER
2015-08-20 10:14:22 +03:00
0ec17fd4d6
daq2-a10gx- parameter changes
2015-08-19 14:56:00 -04:00
0e587dd955
daq2/a10gx-- ad-rst unpack
2015-08-19 13:26:38 -04:00
fdeeef3d77
daq2/a10gx-- intmem to ddr
2015-08-19 13:26:38 -04:00
e760aa424a
daq2/a10gx-- intmem to ddr
2015-08-19 13:26:38 -04:00
413c322145
base/daq2- updates
2015-08-19 13:26:38 -04:00
f40abf171f
cpack- adc_rst added
2015-08-19 13:26:38 -04:00
8cc3aa0865
ddr- 933/233
2015-08-19 13:26:38 -04:00
57cfb7cfb1
hdl/library: Update the IP parameters
...
The following IP parameters were renamed:
PCORE_ID --> ID
PCORE_DEVTYPE --> DEVICE_TYPE
PCORE_IODELAY_GROUP --> IO_DELAY_GROUP
CH_DW --> CHANNEL_DATA_WIDTH
CH_CNT --> NUM_OF_CHANNELS
PCORE_BUFTYPE --> DEVICE_TYPE
PCORE_ADC_DP_DISABLE --> ADC_DATAPATH_DISABLE
CHID --> CHANNEL_ID
PCORE_DEVICE_TYPE --> DEVICE_TYPE
PCORE_MMCM_BUFIO_N --> MMCM_BUFIO_N
PCORE_SERDES_DDR_N --> SERDES_DDR_N
PCORE_DAC_DP_DISABLE --> DAC_DATAPATH_DISABLE
DP_DISABLE --> DATAPATH_DISABLE
PCORE_DAC_IODELAY_ENABLE --> DAC_IODELAY_ENABLE
C_BIG_ENDIAN --> BIG_ENDIAN
C_M_DATA_WIDTH --> MASTER_DATA_WIDTH
C_S_DATA_WIDTH --> SLAVE_DATA_WIDTH
NUM_CHANNELS --> NUM_OF_CHANNELS
CHANNELS --> NUM_OF_CHANNELS
PCORE_4L_2L_N -->QUAD_OR_DUAL_N
C_ADDRESS_WIDTH --> ADDRESS_WIDTH
C_DATA_WIDTH --> DATA_WIDTH
C_CLKS_ASYNC --> CLKS_ASYNC
PCORE_QUAD_DUAL_N --> QUAD_DUAL_N
NUM_CS --> NUM_OF_CS
PCORE_DAC_CHANNEL_ID --> DAC_CHANNEL_ID
PCORE_ADC_CHANNEL_ID --> ADC_CHANNEL_ID
PCORE_CLK0_DIV --> CLK0_DIV
PCORE_CLK1_DIV --> CLK1_DIV
PCORE_CLKIN_PERIOD --> CLKIN_PERIOD
PCORE_VCO_DIV --> VCO_DIV
PCORE_Cr_Cb_N --> CR_CB_N
PCORE_VCO_MUL --> VCO_MUL
PCORE_EMBEDDED_SYNC --> EMBEDDED_SYNC
PCORE_AXI_ID_WIDTH --> AXI_ID_WIDTH
PCORE_ADDR_WIDTH --> ADDRESS_WIDTH
DADATA_WIDTH --> DATA_WIDTH
NUM_OF_NUM_OF_CHANNEL --> NUM_OF_CHANNELS
DEBOUNCER_LEN --> DEBOUNCER_LENGTH
ADDR_WIDTH --> ADDRESS_WIDTH
C_S_AXIS_REGISTERED --> S_AXIS_REGISTERED
Cr_Cb_N --> CR_CB_N
ADDATA_WIDTH --> ADC_DATA_WIDTH
BUFTYPE --> DEVICE_TYPE
NUM_BITS --> NUM_OF_BITS
WIDTH_A --> A_DATA_WIDTH
WIDTH_B --> B_DATA_WIDTH
CH_OCNT --> NUM_OF_CHANNELS_O
M_CNT --> NUM_OF_CHANNELS_M
P_CNT --> NUM_OF_CHANNELS_P
CH_ICNT --> NUM_OF_CHANNELS_I
CH_MCNT --> NUM_OF_CHANNELS_M
4L_2L_N --> QUAD_OR_DUAL_N
SPI_CLK_ASYNC --> ASYNC_SPI_CLK
MMCM_BUFIO_N --> MMCM_OR_BUFIO_N
SERDES_DDR_N --> SERDES_OR_DDR_N
CLK_ASYNC --> ASYNC_CLK
CLKS_ASYNC --> ASYNC_CLK
SERDES --> SERDES_OR_DDR_N
GTH_GTX_N --> GTH_OR_GTX_N
IF_TYPE --> DDR_OR_SDR_N
PARALLEL_WIDTH --> DATA_WIDTH
ADD_SUB --> ADD_OR_SUB_N
A_WIDTH --> A_DATA_WIDTH
CONST_VALUE --> B_DATA_VALUE
IO_BASEADDR --> BASE_ADDRESS
IO_WIDTH --> DATA_WIDTH
QUAD_DUAL_N --> QUAD_OR_DUAL_N
AXI_ADDRLIMIT --> AXI_ADDRESS_LIMIT
ADDRESS_A_DATA_WIDTH --> A_ADDRESS_WIDTH
ADDRESS_B_DATA_WIDTH --> B_ADDRESS_WIDTH
MODE_OF_ENABLE --> CONTROL_TYPE
CONTROL_TYPE --> LEVEL_OR_PULSE_N
IQSEL --> Q_OR_I_N
MMCM --> MMCM_OR_BUFR_N
2015-08-19 14:11:47 +03:00
10d9de39a1
axi_ad9361/tdd: Update the synchronization logic
...
The master will regenerate a sync pulse periodically. The period can be defined by software.
2015-08-19 12:21:23 +03:00
bcee3e04d4
fmcomms2_tdd: Update tdd_enabaled path
...
This line controls the mux, which switch between hdl and software (GPIO) control of the ENABLE/TXNRX pins.
Fix the broken path and change the name from "tdd_enable" to "tdd_enabled".
2015-08-19 12:14:05 +03:00
e221c3b48c
daq2- gt changes
2015-08-17 14:11:58 -04:00
c72cf99562
daq2- gt changes
2015-08-17 14:11:58 -04:00
b84afcdcd1
Merge branch 'master' into dev
...
Conflicts:
library/Makefile
library/axi_ad6676/axi_ad6676_ip.tcl
library/axi_ad9122/axi_ad9122_core.v
library/axi_ad9122/axi_ad9122_ip.tcl
library/axi_ad9144/axi_ad9144_ip.tcl
library/axi_ad9152/axi_ad9152_ip.tcl
library/axi_ad9234/axi_ad9234_ip.tcl
library/axi_ad9250/axi_ad9250_hw.tcl
library/axi_ad9250/axi_ad9250_ip.tcl
library/axi_ad9361/axi_ad9361.v
library/axi_ad9361/axi_ad9361_dev_if_alt.v
library/axi_ad9361/axi_ad9361_ip.tcl
library/axi_ad9361/axi_ad9361_rx_channel.v
library/axi_ad9361/axi_ad9361_tdd.v
library/axi_ad9361/axi_ad9361_tx_channel.v
library/axi_ad9625/axi_ad9625_ip.tcl
library/axi_ad9643/axi_ad9643_channel.v
library/axi_ad9643/axi_ad9643_ip.tcl
library/axi_ad9652/axi_ad9652_channel.v
library/axi_ad9652/axi_ad9652_ip.tcl
library/axi_ad9671/axi_ad9671_constr.xdc
library/axi_ad9671/axi_ad9671_ip.tcl
library/axi_ad9680/axi_ad9680_ip.tcl
library/axi_ad9739a/axi_ad9739a_ip.tcl
library/axi_dmac/axi_dmac_constr.sdc
library/axi_hdmi_tx/axi_hdmi_tx_ip.tcl
library/axi_jesd_gt/axi_jesd_gt_constr.xdc
library/axi_jesd_gt/axi_jesd_gt_ip.tcl
library/axi_mc_speed/axi_mc_speed_constr.xdc
library/common/ad_gt_channel_1.v
library/common/ad_gt_common_1.v
library/common/ad_gt_es.v
library/common/ad_iqcor.v
library/common/ad_jesd_align.v
library/common/ad_rst.v
library/common/altera/ad_xcvr_rx_rst.v
library/common/up_adc_common.v
library/common/up_axis_dma_rx.v
library/common/up_axis_dma_tx.v
library/common/up_clkgen.v
library/common/up_clock_mon.v
library/common/up_dac_common.v
library/common/up_gt.v
library/common/up_hdmi_tx.v
library/common/up_tdd_cntrl.v
library/common/up_xfer_cntrl.v
library/common/up_xfer_status.v
library/util_cpack/util_cpack.v
library/util_cpack/util_cpack_ip.tcl
library/util_dac_unpack/util_dac_unpack_hw.tcl
library/util_jesd_align/util_jesd_align.v
library/util_jesd_xmit/util_jesd_xmit.v
library/util_upack/util_upack_ip.tcl
library/util_wfifo/util_wfifo.v
library/util_wfifo/util_wfifo_constr.xdc
library/util_wfifo/util_wfifo_ip.tcl
projects/arradio/c5soc/system_bd.qsys
projects/common/vc707/vc707_system_bd.tcl
projects/common/zc706/zc706_system_plddr3.tcl
projects/daq2/a10gx/Makefile
projects/daq2/a10gx/system_bd.qsys
projects/daq3/common/daq3_bd.tcl
projects/daq3/zc706/system_bd.tcl
projects/fmcjesdadc1/a5gt/Makefile
projects/fmcjesdadc1/a5gt/system_bd.qsys
projects/fmcjesdadc1/a5gt/system_constr.sdc
projects/fmcjesdadc1/a5gt/system_top.v
projects/fmcjesdadc1/a5soc/system_bd.qsys
projects/fmcjesdadc1/common/fmcjesdadc1_bd.tcl
projects/fmcomms1/ac701/system_bd.tcl
projects/fmcomms1/common/fmcomms1_bd.tcl
projects/fmcomms1/kc705/system_bd.tcl
projects/fmcomms1/vc707/system_bd.tcl
projects/fmcomms1/zc702/system_bd.tcl
projects/fmcomms1/zc702/system_top.v
projects/fmcomms1/zc706/system_bd.tcl
projects/fmcomms1/zc706/system_top.v
projects/fmcomms1/zed/system_bd.tcl
projects/fmcomms1/zed/system_top.v
projects/fmcomms2/ac701/system_constr.xdc
projects/fmcomms2/common/fmcomms2_bd.tcl
projects/fmcomms2/kc705/system_constr.xdc
projects/fmcomms2/kc705/system_top.v
projects/fmcomms2/mitx045/system_top.v
projects/fmcomms2/rfsom/system_constr.xdc
projects/fmcomms2/rfsom/system_top.v
projects/fmcomms2/vc707/system_top.v
projects/fmcomms2/zc706/system_bd.tcl
projects/fmcomms2/zc706/system_constr.xdc
projects/fmcomms2/zc706/system_top.v
projects/fmcomms2/zed/system_top.v
projects/imageon/zc706/system_constr.xdc
projects/motcon2_fmc/common/motcon2_fmc_bd.tcl
projects/motcon2_fmc/zed/system_constr.xdc
projects/motcon2_fmc/zed/system_top.v
projects/usdrx1/a5gt/Makefile
projects/usdrx1/a5gt/system_bd.qsys
projects/usdrx1/common/usdrx1_bd.tcl
Conflicts were resolved using 'Mine' (/dev).
2015-08-17 15:15:58 +03:00
17b2a9f121
Merge branch 'master'
...
Merge master into release to sync the index files. The two changes are just mode changes. There aren't any functional changes in this commit!
2015-08-17 10:09:07 +03:00
f08633c0d5
fmcomms2: Add GPIO to the c5soc project
2015-08-13 18:14:39 +03:00
c200fc8019
usdrx1: Updated a5gt project to Quartus 15
2015-08-12 10:20:58 +03:00
489b31e929
ad9434_fmc: DMAC's destination clock must be more than or equal to adc_clk/4 (125 Mhz)
...
DMAC's destination clock set to 200Mhz
2015-08-10 18:00:24 +03:00
10a3ce96fe
ad9434_fmc: DMAC's destination clock must be more than or equal to adc_clk/4 (125 Mhz)
...
DMAC's destination clock set to 200Mhz
2015-08-10 17:57:52 +03:00
afb9911b6e
Makefiles: Updated makefiles
2015-08-06 19:50:50 +03:00
d2c99acae8
fmcomms2/TDD: Update synchronization interface
...
Synchronization is done by a simple req/ack interface between a master and slave terminal.
2015-08-06 15:14:36 +03:00
cfc4046821
fmcomms2: Add a synchronization interface for TDD mode.
...
Supported carrier are ZC706 and RFSOM.
The synchronization pulse is automatically generated by the master terminal, when TDD mode is enabled.
By default a terminal is slave, software must write 0x01 into TDD register 0x50.
2015-07-29 14:10:56 +03:00
8e631e56d6
fmcomms2: Add a synchronization interface for TDD mode.
...
Supported carrier are ZC706 and RFSOM.
The synchronization pulse is automatically generated by the master terminal, when TDD mode is enabled.
By default a terminal is slave, software must write 0x01 into TDD register 0x50.
2015-07-28 14:42:54 +03:00
36f71ea59b
fmcjesdadc1: common altera, fixed dmac configuration and connection. Connected reset for cpack
2015-07-28 12:33:24 +03:00
0422c87846
a5soc/base- remove hdmi, led/switchs to gpio
2015-07-27 12:08:33 -04:00
2ca2bf9383
a5soc- all hps clocks
2015-07-27 12:08:33 -04:00
e488ba0287
a5soc- remove hdmi core
2015-07-27 12:08:32 -04:00
0c5958091e
fmcjesdadc1/a5soc- base/fmc split
2015-07-27 12:08:32 -04:00
0a5dc938cd
fmcjesdadc1/a5soc- base/fmc split
2015-07-27 12:08:32 -04:00
f5f9ec38e8
a5soc- base/fmc split
2015-07-27 12:08:32 -04:00
58e0884ff9
a5soc- board qsys file
2015-07-27 12:08:32 -04:00
4d7ff0ed15
a5gte: Update ethernet connections
2015-07-27 16:05:26 +03:00
31ab81d627
a5gt: Updated ethernet clock constraints
2015-07-27 16:02:51 +03:00
797d679c72
fmcomms2: Updated c5soc project with the latest cores. Tested with Quartus 15.0
2015-07-24 16:43:33 +03:00
816238bb6c
fmcjesdadc:A5gt, decreased destination bus width for DMAs to 256. Increased DMA FIFO to 32
...
With lower buswidth, if all 4 channels are captured some samples are lost
With fifo size of 64, there are timing violations in the DMAC
With this configuration, 65536 samples could be captured from all 4 channels with no sample lost
Because of the DMAC destination bus is 256, the number of samples to be captured must be a multiple of 16, otherwise the system will freeze. This will be corrected in software
2015-07-24 15:31:19 +03:00
289e73660b
removed- xcvr is now part of qsys
2015-07-23 15:26:51 -04:00
fb648ab6f5
moved to qsys
2015-07-23 15:26:21 -04:00
3ccf1bef36
base system modifications
2015-07-23 15:23:10 -04:00
a1733238df
fmcjesdadc1- base/board split up
2015-07-23 15:21:53 -04:00
3ea60bca5d
fmcjesdadc1: a5gt, design working with quartus 15.0
...
- added cpack to the design
- removed 166 MHz clock as it is not needed. DMA destination is 512 bits
- removed clock bridge between DMA and DDR
2015-07-23 18:11:53 +03:00
d8e2196c75
fmcjesdadc1- board qsys
2015-07-22 15:44:04 -04:00
d66387f482
fmcjesdadc1- board qsys
2015-07-22 15:23:39 -04:00
3e2712cf18
a5gt-base: initial updates
2015-07-22 15:22:22 -04:00
64070b6f27
a5gt- base system
2015-07-22 15:04:59 -04:00
b325c0fc01
fmcomms2_zc702: Add SPI and GPIO interface for FREQCVT
2015-07-22 10:22:07 +03:00
28aea82952
fmcomms2_zc702: Add SPI and GPIO interface for FREQCVT
2015-07-22 10:16:04 +03:00
b4eac232db
a10gx- move cores inside qsys
2015-07-21 11:06:45 -04:00
fcc298d837
a10gx- move cores inside qsys
2015-07-21 11:06:17 -04:00
b3102b5095
daq2/a10gx-- xcvr+base changes
2015-07-21 11:01:45 -04:00
445c4c835d
daq2-bd: xcvr components
2015-07-21 10:54:23 -04:00
08e46c5ff2
a10gx-base: data-master connections
2015-07-21 10:53:54 -04:00
97b8468819
daq2- constraints
2015-07-20 09:32:17 -04:00
1d6a77049d
daq2- base/board split
2015-07-20 09:31:57 -04:00
4b8d764852
daq2- base system modifications
2015-07-20 09:31:44 -04:00
da2e7acacb
daq2- separate base/board systems
2015-07-20 09:31:15 -04:00
Rejeesh Kutty
Istvan Csomortani
Lars-Peter Clausen
Adrian Costina