Commit Graph

19 Commits (3adefaddfd491ee4bd9ce353ecd97fe3772a5578)

Author SHA1 Message Date
Adrian Costina 844a848d2d pluto: Removed interconnects to HP ports to reduce utilization 2019-04-15 17:49:11 +03:00
Laszlo Nagy 4ce153e6e1 all/system_top.v: loopback gpio lines
Create loopback on unused GPIO lines since Linux may rely on it.
2018-10-04 14:19:37 +03:00
Laszlo Nagy 31318cf311 all/system_top.v: drive unused gpio inputs with zero
The loopback on the unused gpio inputs consumes routing resources
while does not gives any value for the software.

Connect these lines to zero instead.
2018-08-10 17:00:11 +03:00
AndreiGrozav ebae8bf8c1 Remove interrupts from system_top for all xilinx projects
- remove interrupts from system_top
- for all suported carriers:
	- remove all interrupt bd pins
	- connect to GND all initial unconnected interrupt pins
- update ad_cpu_interrupt procedure to disconnect a interrupt from GND
before connectiong it to another pin.
2018-08-10 10:10:58 +03:00
Lars-Peter Clausen 377247a434 Regenerate project Makefiles using the new shared Makefile includes
This reduces the amount of boilerplate code that is present in these
Makefiles by a lot.

It also makes it possible to update the Makefile rules in future without
having to re-generate all the Makefiles.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-04-11 15:09:54 +03:00
Istvan Csomortani 425e803364 license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
Istvan Csomortani a740b6012f Make: Use $(MAKE) for recursive make commands
This commit should resolve the issue #64.

Recursive make commands should always use the variable MAKE, not the explicit
command name ‘make’.
2018-03-07 07:40:19 +00:00
Adrian Costina b7ca17f02b scripts: Change adi_project_create to adi_project_xilinx for creating xilinx projects 2017-06-07 12:06:50 +03:00
Istvan Csomortani 84b2ad51e2 license: Add some clarification to the header license 2017-05-31 18:18:56 +03:00
Istvan Csomortani 85ebd3ca01 license: Update license terms in hdl source files
Fix a few gramatical error, fix the path of the top level license
files.
2017-05-29 09:55:41 +03:00
Istvan Csomortani 9055774795 all: Update license for all hdl source files
All the hdl (verilog and vhdl) source files were updated. If a file did not
have any license, it was added into it. Files, which were generated by
a tool (like Matlab) or were took over from other source (like opencores.org),
were unchanged.

New license looks as follows:

Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.

Each core or library found in this collection may have its own licensing terms.
The user should keep this in in mind while exploring these cores.

Redistribution and use in source and binary forms,
with or without modification of this file, are permitted under the terms of either
 (at the option of the user):

  1. The GNU General Public License version 2 as published by the
     Free Software Foundation, which can be found in the top level directory, or at:
https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html

OR

  2.  An ADI specific BSD license as noted in the top level directory, or on-line at:
https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
2017-05-17 11:52:08 +03:00
Adrian Costina 8e0c87e089 pluto: cleaned up some warnings 2017-04-18 10:34:13 +03:00
Adrian Costina c419b0042b pluto: ip automatic version update 2017-04-14 16:55:07 +03:00
Rejeesh Kutty 8063ba2b66 make updates 2017-03-20 16:05:18 -04:00
Rejeesh Kutty 9b6dd27c23 ad9361- delay initialization 2017-03-15 12:06:59 -04:00
Rejeesh Kutty 1b3f752c3d pzsdr1/pzsdr2/pluto- add iodelay report 2017-03-10 12:55:22 -05:00
Adrian Costina a569b6bf0c pluto: Interpolation, connect fifo_rd_valid to s_axis_data_tvalid 2017-02-13 18:08:52 +02:00
Rejeesh Kutty f64b44c8ac sdrstk2pluto- contents 2016-11-11 13:52:57 -05:00
Rejeesh Kutty 2ececad58c sdrstk-2-pluto 2016-11-11 13:49:04 -05:00