Commit Graph

4429 Commits (3b34e8b594ab22026043dde414812f0bfeafd65a)

Author SHA1 Message Date
Istvan Csomortani 3b34e8b594 up_clock_com: Fix the false path definitions for CDCs 2018-04-11 15:09:54 +03:00
AndreiGrozav 502989c25f jesd_rst_gen:constraints: Remove invalid false path definitions
The constraint where added to remove timing problems on the reset path.

The constraint paths do not match anymore. The resets are used in a synchronous
way so we don't need the timing exceptions anyway.

Projects affected by this change:
  - daq3
  - adrv9739
  - ad6676evb
  - fmcadc5
  - daq2/kcu105
  - fmcadc2
  - adrv9371x
  - fmcomms11/zc706
  - fmcjesdadc1
2018-04-11 15:09:54 +03:00
Istvan Csomortani 2356694a50 kc705/vc707/kcu105: Fix axi_spi related critical warning
By default every base design has a SPI interface (hard or soft). In
case of soft IPs (xilinx), the input registers of the interface by default have
the IOB attribute set to TRUE. If the interface are not used, the tool will
generate a critical warning, stating that IOB registers are not connected to
an IO buffer.
The following constraints are disabling the above setup for every base
design, which using a soft SPI IP.
2018-04-11 15:09:54 +03:00
AndreiGrozav c313c67585 axi_adcfifo_constr.xdc: Add missing backslash to command 2018-04-11 15:09:54 +03:00
Istvan Csomortani d81f605ae9 axi_ad9162: Fix code alignment, no functional changes 2018-04-11 15:09:54 +03:00
Laszlo Nagy fe2b43ddd9 base:constraint: Setting Configuration Bank Voltage Select
Set the properties to mirror the hardware configuration so
the Vivado tools can provide warnings if there are any conflicts
between configuration pin settings, such as an IOSTANDARD
on a multi-function configuration pin that conflicts with the
configuration voltage.
see:
https://www.xilinx.com/support/documentation/user_guides/ug570-ultrascale-configuration.pdf

The following base constraints were updated:
 - kcu105
 - kc705
 - vc707
 - ac701
2018-04-11 15:09:54 +03:00
Istvan Csomortani 758c617c77 common/up_* : Make up_rstn synchronous to up_clk
The up_rstn is driven by s_axi_resetn, which is generated by a
Processor System Reset module. (connected to port peripheral_aresetn)
Therefor using this reset signal as an asynchronous reset is redundant,
and a bad design practice at the same time. Asynchronous reset should be
used if it's inevitable.
2018-04-11 15:09:54 +03:00
AndreiGrozav 57a61f0635 scripts:adi_project: Update ZCU102 device package and board files
ZCU102 is a fairly new board and gets additional support in 2017.4.
2018-04-11 15:09:54 +03:00
AndreiGrozav dd8d6f90ee zcu102:all_projects: Delete required version tcl variable
All the ZCU102 projects will use the default tool version.
This setup was a temporary exception for hdl_2017_r1 release.
2018-04-11 15:09:54 +03:00
Istvan Csomortani 0026617033 scripts:adi_project: Use default strategies for synth and impl
To reduce compilation time use default stratagies for synthesis and
implementation. If a project will require custom strategies, enable it
just for that particular project.

This modification will affect both Intel and Xilinx projects.
2018-04-11 15:09:54 +03:00
Adrian Costina 8234ba1029 scripts:adi_ip: Update web address format
Change format for web address so that IP GUI considers it valid
2018-04-11 15:09:54 +03:00
Istvan Csomortani 7c04e36656 scripts: Message severity changes on Vivado
Vivado sometimes generates semi-valid or invalid warnings and critical warnings.
In the past these messages were silenced, by changing its message severity.
These setups were scattered in multiple scripts. This commit is an attempt
to centralize it and make it more maintainable and easier to review it.
2018-04-11 15:09:54 +03:00
Istvan Csomortani 47e95fc4a9 scripts: Update tools for the next release
The next supported tool versions are:
  + Vivado 2017.4.1
  + Quartus 17.1
2018-04-11 15:09:54 +03:00
Istvan Csomortani 3e18291d39 usb_fx3: Delete unused project 2018-04-11 15:09:54 +03:00
Istvan Csomortani 377848ef52 cftl: Delete unused projects and libraries 2018-04-11 15:09:54 +03:00
Istvan Csomortani bee392253b jesd204:tb: Fix the loopback_tb test bench
The jesd204_rx instantiation contained a port that did not exist. (phy_ready)
2018-03-28 15:19:18 +01:00
Istvan Csomortani 63780f8179 README: Remove the Documentation section, it's redundant 2018-03-07 12:28:40 +00:00
Istvan Csomortani 48b2b034a5 README: General rework and add more embedded links to wiki
+ Add more links to wiki
  + Add a software section with link to no-OS and Linux
  + Change the 'Development flow' to 'Which branch should I use?'
  + Add a documentation section
2018-03-07 12:28:40 +00:00
Istvan Csomortani 2c726ce45a README: A generic README update 2018-03-07 12:28:40 +00:00
Adrian Costina 9baf910339 axi_logic_analyzer: Fix push-pull/open-drain selection 2018-03-07 10:19:51 +02:00
Istvan Csomortani a740b6012f Make: Use $(MAKE) for recursive make commands
This commit should resolve the issue #64.

Recursive make commands should always use the variable MAKE, not the explicit
command name ‘make’.
2018-03-07 07:40:19 +00:00
Lars-Peter Clausen e95f1b282e Remove unused Q_OR_I_N parameter from JESD204 ADC cores
The cores that handle the JESD204 ADC cores do not feature IQ correction
logic. The Q_OR_I_N parameter for the channel modules is unused, so remove
it.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-02-20 16:33:16 +01:00
Lars-Peter Clausen 0c2fad54d7 Remove unused IO_DELAY_GROUP parameter from JESD204 ADC cores
The cores that handle the JESD204 ADC converters do not feature any direct
IO and subsequently no IO-delay blocks either. Remove the unused
IO_DELAY_GROUP parameter.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-02-20 16:33:16 +01:00
Lars-Peter Clausen 041e448083 ad6676: Fix OUT_CLK_SEL configuration
The script specifies the OUT_CLK_SEL and SYS_CLK_SEL parameter values as
binary numbers. But the tools will interpret them as decimal number
resulting in the wrong selection for OUT_CLK_SEL. Specify the parameter
values as decimal values to avoid this.

This is not a critical issue since software will overwrite this setting at
system boot-up. But it should be fixed anyway.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-02-16 13:32:50 +01:00
Lars-Peter Clausen 8b6d69747b fmcjesdadc1: Fix OUT_CLK_SEL configuration
The script specifies the OUT_CLK_SEL and SYS_CLK_SEL parameter values as
binary numbers. But the tools will interpret them as decimal number
resulting in the wrong selection for OUT_CLK_SEL. Specify the parameter
values as decimal values to avoid this.

This is not a critical issue since software will overwrite this setting at
system boot-up. But it should be fixed anyway.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-02-16 13:32:50 +01:00
Lars-Peter Clausen ce8bcfd192 fmcjesdadc1: Remove wire that is a redeclaration of a port
Fixes the following warning:
	[Synth 8-2611] redeclaration of ansi port rx_sysref is not allowed

This is a leftover of commit 1c23cf4621 ("all: Update verilog files to
verilog-2001").

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-02-16 13:32:26 +01:00
Lars-Peter Clausen 271731ebc8 fmcomms5: Remove wires that are redeclarations of ports
Fixes the following warnings:
	[Synth 8-2611] redeclaration of ansi port txnrx_0 is not allowed
	[Synth 8-2611] redeclaration of ansi port enable_0 is not allowed
	[Synth 8-2611] redeclaration of ansi port enable_1 is not allowed
	[Synth 8-2611] redeclaration of ansi port txnrx_1 is not allowed

This is a leftover of commit 1c23cf4621 ("all: Update verilog files to
verilog-2001").

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-02-16 13:32:26 +01:00
AndreiGrozav 64c8fd7e5e axi_clkgen: add ultrascale series support 2018-02-13 17:33:38 +02:00
AndreiGrozav 8403ff17ec adrv9371x/kcu105: Use ultrascale type primitives in axi_clkgen IP 2018-02-13 17:33:38 +02:00
AndreiGrozav 2302d3516d adrv9371x:kcu105: Update transceiver configuration 2018-02-13 17:33:38 +02:00
Adrian Costina 73ef0fb48c adrv9371x: kcu105: Fix transceiver and clock placement 2018-02-13 17:33:38 +02:00
Istvan Csomortani e23121fe38 Merge branch hdl_2017_r1 2018-02-06 10:46:23 +00:00
Istvan Csomortani bf3ba4426c fmcomms11: Update the SPI IO definitions 2018-01-29 18:48:31 +02:00
Istvan Csomortani 55b4603e60 fmcomms11: Update the clock tree
- one single reference clock for both rx and tx channels
  - delete the SYSREF inputs
  - update the IO location of the usr_clk
2018-01-29 18:44:15 +02:00
Istvan Csomortani ff562e7165 fmcomms11: Delete trailing whitespaces 2018-01-29 17:46:54 +02:00
Matt Fornero 3e7399913f axi_dmac: Include TLAST in AXIS slave port
Bundle the TLAST signal in with the other AXIS slave signals to enable
easier connection between AXIS devices that use TLAST

Signed-off-by: Matt Fornero <matt.fornero@mathworks.com>
2018-01-23 17:43:48 +01:00
Lars-Peter Clausen c6073954d9 axi_dmac: Add limited TLAST support for streaming AXI source interface
Add some limit TLAST support for the streaming AXI source interface. An
asserted TLAST signal marks the end of a packet and the following data beat
is the first beat for the next packet.

Currently the DMAC does not support for completing a transfer before all
requested bytes have been transferred. So the way this limited TLAST
support is implemented is by filling the remainder of the buffer with 0x00.

While the DMAC is busy filling the buffer with zeros back-pressure is
asserted on the external streaming AXI interface by keeping TREADY
de-asserted.

The end of a buffer is marked by a transfer that has the last bit set in
the FLAGS control register.

In the future we might add support for transfer completion before all
requested bytes have been transferred.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-01-23 17:43:48 +01:00
Lars-Peter Clausen da28ee3cce axi_ad9361: xilinx LVDS interface: Restore previous feedback clock polarity
Commit ff50963c7f ("axi_ad9361- altera/xilinx reconcile- may be broken-
do not use") inverted the polarity of the TX feedback clock.

This exposed some issues in the existing drivers which can cause the
interface tuning to fail randomly under certain conditions.

To keep backwards compatibility with existing drivers restore the previous
behavior.

A separate fix will be applied to the drivers that resolves the issue that
has been exposed by the polarity inversion. So that interface calibration
works reliably under all conditions.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-01-19 18:17:50 +01:00
AndreiGrozav 92321f0534
ad9434: Specified DEVICE_TYPE parameter options 2018-01-19 14:13:37 +02:00
AndreiGrozav 28830b4b66
axi_ad9434.v Add description for parameter 2018-01-18 15:52:11 +02:00
AndreiGrozav d44f7d1e4f axi_ad9434: Fix bad parameter definition
Assigning the value of a local parameter(localparam) to a parameter
will end up with a conflict(not highlighted by the tool). In this
case, the parameter type was defined as a string instead of an
integer. Furthermore, this scenario leads to an undesired choice
between primitive types.
2018-01-18 14:46:08 +02:00
Michael Hennerich 2e59a70cdd adrv9371: Increase FCLK2 to 200MHz to support max sampling rates
This fixes an issue seen when using 307.2 MSPS on the Observation RX.

Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
2018-01-09 15:20:06 +01:00
Istvan Csomortani 3e3955ce91 avl_dacfifo: Fix avl_address generation
+ Define address limit at 2GByte
  + Address is WORD aligned, increment accordingly
2017-12-15 12:17:47 +00:00
Istvan Csomortani 60d2fb939d avl_dacfifo: Control the avl_burstcount inside the FSM 2017-12-15 08:56:57 +00:00
Istvan Csomortani b8e8410cbc avl_dacfifo: Fix the last address buffer control 2017-12-15 08:56:57 +00:00
Istvan Csomortani aaff5a8d6a avl_dacfifo: dma_last_beats is transfered to avalon clock domain, without conditioning
The dma_last_beats is used by the Avalon Memory Mapped interface
controller, to define the last burst length.
Its value get stable after the last valid data of the DMA interface, and staying
stable until the positive edge of the DMA's xfer_req.

No need to condition the transfer of this register to avalon clock
domain.
2017-12-15 08:55:01 +00:00
Istvan Csomortani 3b4aaec926 daq2: Data underflow of DAC FIFO is monitored by the device core 2017-12-09 10:52:05 +00:00
Istvan Csomortani 6bbf1ae83c avl_dacfifo: End of burst is not always end of a transaction
The XFER_END state defines the end of a transaction, when the entire
data set is written or read to/from the DDRx memory.
A transaction can contain multiple Avalon bursts. Make sure that the FSM
goes back into staging phase at the end of each burst; also define a
signals which indicate the end of each burst for control.
2017-12-09 09:56:33 +00:00
Luca Ceresoli ba24909a25 axi_streaming_dma_rx_fifo: fix period_count clock and TLAST
The period_count should be updated once per clock cycle. This is not
enforced with the current implementation, which probably leads to
period_count being decremented on both m_axis_aclk edges.

A problem observed due to this is that the m_axis_tlast output is not
asserted or is asserted for a too short time for the consumer to
detect it.

Fix by letting the decrement (and thus the m_axis_tlast toggling)
happen only on the rising edge of the m_axis_aclk clock.

Signed-off-by: Luca Ceresoli <luca@lucaceresoli.net>
2017-12-05 13:04:46 +00:00
Adrian Costina 386febaa7e fmcadc5: Allow JESD reset from the ADC core, useful for synchronization 2017-11-29 16:03:00 +02:00