5 Commits (3b58785368e21e4062b18c77f2a61fe1b879854f)

Author	SHA1	Message	Date
Adrian Costina	19ef85cec3	vc707: Changed mig project to use BANK_ROW_COLUMN, as it seems this mode gives best performance	2015-04-28 17:15:58 +03:00
Adrian Costina	69326a72ef	VC707: Updated base design	2015-03-20 18:20:44 +02:00
Istvan Csomortani	aa7b0bb4dd	VC707 basesys: General fixes, actual status: working ... - Add an auxiliary cpu interconnect - Add an auxiliary interrupt concatenation module - Add new MIG file, current frequency of the DDR interface is 100 Mhz - Memory interconnect optimisation strategy is 'Maximize Performance'	2014-03-24 13:07:48 +02:00
Istvan Csomortani	75963ab376	Initial check in of VC707 base project ... - All source files for the VC707 base project - Update the common base system to the new naming convention	2014-03-10 17:26:17 +02:00
Rejeesh Kutty	ddac1a8834	added common board files	2014-02-28 21:17:01 -05:00