Dual clock mode is introduced in link layer to support different
datapath widths on the transport layer than on physical layer.
- Link clock : lane rate / 40 for input datapath width of 4 octets 8b10b
- Device clock : Link clock * input data path width / output datapath width
Supports four clock configurations, single or dual clock mode with or
without external device clock.
The configuration interface reflects the dual clock domain.
Support multiple clock monitors in a block.
Before this change the clock monitor had to be named with a fix name
preventing multiple instances of the clock monitor.
Add parameter that describes interface to link layer, this must be
integer multiple of octets per frame.
Add parameter that describes interface to user/DMA, this must be
multiple of bytes so software can process the samples easier.
Make synthesis parameters accessible for the drivers.
Rework implementation to reflect the parameters of the actual core and
not of the AXI interfacing core.
To support deterministic latency with non-power of two octets per frame
(F=3,6) the interface width towards the transport layer must be resized
to match integer multiple of frames.
e.g Input datapath width = 4; Output datpath width = 6;
for F=3 one beat contains 2 frames
for F=6 one beat contains 1 frame
The width change is realized with a gearbox.
Due the interface width change the single clock domain core is split
in two clock domains.
- Link clock : lane rate / 40 for input datapath width of 4 octets 8b10b
- lane rate / 20 for input datapath width of 8 octets 8b10b
- lane rate / 66 for input datapath width of 8 octets 64b66b
- Device clock : Link clock * input data path width / output datapath width
Interface to transport layer and SYSREF handling is moved to device clock domain.
The configuration interface reflects the dual clock domain.
If Input and Output datapath width matches, the gearbox is no longer
required, a single clock can be connected to both clocks.
In order to keep resource utilization low and for better timing closure
allow disabling of the character replacement logic.
If the parameter is set the frame alignment monitoring is limited to links
where scrambling is on.
Add support to JESD204 RX and TX core for 8-byte 8b/10b link mode,
and frame alignment character replace/insert with or without scrambling.
Add support for xcelium simulator to jesd204/tb
Increased cores minor version.
There are boards (e.g. AD4630-24) which take the SCLK and echo back to
the FPGA through a level shifter - doing this removes the effect of
round-trip timing delays from the level shifter. This is commonly done
whenever isolators are used since they are very slow.
By setting the ECHO_SCLK parameter to 1, the IP will use the incoming
echoed SCLK clock to latch the SDI line(s). The sdi_data_valid is still
synchronous to the SPI clock, and it's generated after the last valid
SDI latch.
The designer's responsibility is to time the SDI shift registers in order to
respect the design requirements.
The new REG_PRBS_CNTRL and REG_PRBS_STATUS registers expose controls of internal
PRBS generators and checkers allowing the testing the multi-gigabit serial link
at the physical layer without the need of the link layer bringup.
In phase aligned mode the fPLL uses an external feedback path to better
align the phase of the PLL output to the phase of the external reference
clock.
This mode is required for deterministic latency to be able to sample SYSREF
which is source synchronous to the external reference clock signal.
So far phase aligned mode had been disabled since manual PLL calibration
would fail in this mode under certain (unknown) circumstances and dynamic
reconfiguration of the PLL would not work.
The latest Intel Arria 10 transceiver datasheet contains instructions for
the proper calibration sequence to make it work when the PLL is configured
for phase aligned mode. Software has been updated accordingly, so enable
phase aligned mode.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Refactor the AXI4 stream FIFO implementation.
- Define a single address generator which supports both single and double
clock mode. (synchronous and asynchronous)
- Fix FIFO status bits (empty/full). NOTE: In asynchronous mode the
flags can have a several clock cycle delay in function of the upstream/downstream
clock ratio.
- In synchronous none FIFO mode (ADDRESS_WIDTH==0), the module acts as
an AXI4 stream pipeline.
Allow channels received from dma to re-map to other channels, e.g. allowing
broadcasting the same channel to all channels.
The feature is selectable with synthesis parameter and disabled by default.
Istvan Csomortani
Laszlo Nagy
Matt Blanton
sergiu arpadi
Lars-Peter Clausen
AndreiGrozav