4 Commits (3bf7b6c80f7fde085526c8a9732b2e47ad27410c)

Author	SHA1	Message	Date
Rejeesh Kutty	d3050abd3e	rfifo/upack- changes	2017-07-28 16:18:54 -04:00
Istvan Csomortani	ac2e5a9dac	constraints: Update constraints ... Xilinx recommends that all synchronizer flip-flops have their ASYNC_REG property set to true in order to preserve the synchronizer cells through any logic optimization during synthesis and implementation.	2017-02-24 13:43:32 +02:00
Rejeesh Kutty	1df942b752	rfifo- buffer 1 seg before read	2016-07-12 10:24:22 -04:00
Rejeesh Kutty	31671bf9d5	util_rfifo: constraints	2016-05-16 12:19:38 -04:00