297e885981
library- drp moved to up-clock domain
2015-06-01 14:52:52 -04:00
660c84e01c
axi_ad9434 : Update the IO delay interface
2015-05-22 19:47:09 +03:00
4b19646ed9
ad9434_fmc: Fix samples order.
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Four consecutive samples were reversed.
2014-10-21 16:34:28 +03:00
bfa17844ff
ad_serdes_in: General update
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Added a parameter for option SDR / DDR mode, added a parameter for parallel data width.
Note: default IF_TYPE is SDR and default PARALLEL_WIDTH is 8
2014-10-07 17:42:27 +03:00
d5f4991e26
ad9434: Merge the ad9434_if interface data outputs into one single bus
2014-09-25 16:45:12 +03:00
079ed0ffb3
ad_serdes_in: Update the serdes_in module
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Add additional IDELAY block before the ISERDES. Delet the IDDR blocks. Be aware, the ISERDES block are running in DDR mode. If the interface is SDR the maximum parallel data width is 4.
2014-09-25 16:40:29 +03:00
683561b67d
AD9434: Initial check in of the library and project with ZC706
2014-09-24 18:27:17 +03:00
Rejeesh Kutty
Istvan Csomortani