Commit Graph

14 Commits (3c6d19d33dada4ec53f3f1e4f0c31198da50f1e3)

Author SHA1 Message Date
Lars-Peter Clausen c372064302 Add .gitattributes file
Add .gitattributes file which sets up the eol encoding handling. This will
make sure that we get a uniform eol encoding across different operating
systems.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-07-01 18:43:51 +02:00
Adrian Costina 293ec6a319 fmcomms2: c5soc project updated to 14.1 2015-05-08 17:44:16 +03:00
Lars-Peter Clausen d8651cdd2e fmcomms2: c5soc: Set dac_util_unpack number of channels to 4
We only do have 4 channels in this design. Reducing the number of supported
channels for the dac_util_unpack core to 4 from 8 lowers the DMA alignment
requirement from 128bit to 64bit.  We need this since applications only
expect a DMA alignment requirement of 64bit.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-09-12 16:15:12 +02:00
Lars-Peter Clausen ecc498313c fmcomms2: c5soc: Connect ADC, DAC and VGA DMA to different bridge interconnects
We have enough bridge interconnect to give each DMA its own, so use them.
This makes sure that they do not interfere with each others transfers to
much. The SDRAM controller side of the FPGA2SDRAM bridges FIFO runs at a
much faster frequency then what we are able to use in the fabric. So its
better to do the arbitration on that side of the bus to make sure that we
can utilize the buses in the FPGA fabric to the maximum for each DMA core.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-09-12 16:14:07 +02:00
Adrian Costina 61f21a17b3 fmcomms2:c5soc project upgraded with util_dac_unpack 2014-09-11 15:13:09 -04:00
Lars-Peter Clausen 328205c31d fmcomms2: c5soc: Set DMA transfer length to 24 bits
14 bits is a bit to low and we use 24 bits everywhere else as well.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-09-09 15:05:06 +02:00
Lars-Peter Clausen 50faf0c53a Remove executable flags from non-exectuable files 2014-09-09 15:05:06 +02:00
dbogdan 5a42c10233 projects/fmcomms2/c5soc: Added video output. HPS SPI was replaced by 3 Wire SPI. 2014-08-27 21:46:23 +03:00
Rejeesh Kutty 280260e54c c5soc: dmac separated slave and master id widths 2014-08-22 09:08:54 -04:00
Rejeesh Kutty 59759a8ab3 c5soc: working hdl version 2014-07-24 20:51:41 -04:00
Rejeesh Kutty 2955b9db78 fifo2s: flush if no request, c5soc: 14.0 2014-07-15 16:25:33 -04:00
Adrian Costina 39ac29bb01 AD9361: Altera, modified address width so that all registers are accessible
Modified qsys project with the new address span
2014-07-08 10:41:51 +03:00
Rejeesh Kutty a388ccab0a fmcomms2/c5soc: initial checkin 2014-07-02 14:56:00 -04:00
Rejeesh Kutty 9a08189b93 c5soc: initial a5soc copy 2014-07-01 13:09:38 -04:00