Commit Graph

19 Commits (3c6d19d33dada4ec53f3f1e4f0c31198da50f1e3)

Author SHA1 Message Date
Lars-Peter Clausen c372064302 Add .gitattributes file
Add .gitattributes file which sets up the eol encoding handling. This will
make sure that we get a uniform eol encoding across different operating
systems.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-07-01 18:43:51 +02:00
Adrian Costina 3d86f140e5 usdrx1: Removed ILA as the ports from axi_jesd_gt were removed 2015-06-10 10:56:55 +03:00
Rejeesh Kutty 71b5004b25 projects- drp moved to up-clock domain 2015-06-01 14:57:59 -04:00
Rejeesh Kutty 4927ca85c2 projects- jesd-align port name change 2015-05-20 14:24:26 -04:00
Adrian Costina e332fa01c8 ad6676evb, daq2, fmcadc2, fmcjesdadc1, usdrx1: Updated jesd reset connection 2015-04-30 12:11:46 +03:00
Adrian Costina 037484e1d0 usdrx1: Updated project to the latest framework 2015-03-25 17:39:51 +02:00
Istvan Csomortani 4ea86de4db usdrx1_zc706: Update interrupts. 2014-11-27 14:03:54 +02:00
Istvan Csomortani d1af4d2951 usdrx1_fmc: Fix GT lane number definition. 2014-11-27 14:03:10 +02:00
Adrian Costina a0d27a117c usdrx1: Updated project with new synchronization mechanism. Fixed timing constraints 2014-10-22 13:20:44 +03:00
Istvan Csomortani 17675863e0 all_projects: Fix the interrupt connections to preserve IRQ layout 2014-10-22 11:48:08 +03:00
Adrian Costina 8934a66013 usdrx1: Update project so that the AD9671 cores can be synchronized 2014-10-13 17:06:40 +03:00
acostina 296983707b usdrx1: Updated project to 2014.2 2014-09-23 22:45:50 -04:00
acostina 5af2474d51 usdrx1: axi_ad9671 / axi_jesd_gt added signal for frame synchronization 2014-09-23 22:44:33 -04:00
Adrian Costina bdf01738a1 ultrasound: disconnected ADN4670 chips from SPI lines.
Connected everything to ground so that the the clock selected is 0 and all outputs are enabled
2014-09-23 22:30:42 -04:00
Adrian Costina d33fb07587 usdrx1: Modified the GPIO assignments so that board specific GPIOs start from GPIO 32.
GPIOs for which the directions is known, have been specifically assigned.

The SPI clock has been changed to a lower frequency.
2014-09-16 15:56:19 -04:00
Adrian Costina a773cc4992 usdrx1: updated project
ad_jesd_align wasa updated to be able to work with frames that have more than 4 octets per frame
2014-09-01 15:18:39 +03:00
Adrian Costina 6e444559b5 usdrx1: global clock fix 2014-06-10 18:09:49 +03:00
Rejeesh Kutty 96541f0a7f usdrx1: zc706 updated for usdrx1 2014-04-10 11:05:13 -04:00
Rejeesh Kutty 6f36f74eea usdrx1: common board files 2014-04-10 11:05:11 -04:00