Commit Graph

2223 Commits (3d8e05ac170d16f9dadefe938ec5463d7cc31445)

Author SHA1 Message Date
Rejeesh Kutty 3db1050e91 pzsdr2/ccfmc: enable eth1 mdio 2017-05-22 13:38:36 -04:00
Rejeesh Kutty f09b902609 usdrx1- spi/mlo fixes 2017-05-22 13:22:44 -04:00
Adrian Costina 12930c8470 motcon2_fmc: Explicitly assign ETH0 MDIO to EMIO 2017-05-22 18:53:00 +03:00
Rejeesh Kutty 0eaa98370e fmcadc2/vc707- spi clock reg can't be on iob 2017-05-19 15:22:33 -04:00
Rejeesh Kutty eb7171e212 daq3/kcu105- reorder refclk constraints 2017-05-19 11:41:45 -04:00
Rejeesh Kutty 36037a76f8 kcu105- vivado now depends on order of constraints? 2017-05-19 11:21:36 -04:00
Rejeesh Kutty 0b3b1e6c76 kcu105- remove ethernet delay ctrl false path 2017-05-19 11:21:36 -04:00
Lars-Peter Clausen e033d6c48e m2k: Refresh Makefile
The util_cpack core is currently not used by the M2K project. Refresh the
Makefiles to reflect this.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-19 15:33:26 +02:00
Rejeesh Kutty f3959cb5b9 zcu102- 2016.4 updates 2017-05-18 14:17:20 -04:00
Rejeesh Kutty 4f0accbbfa adrv9371x fix dacfifo name 2017-05-18 12:54:14 -04:00
Rejeesh Kutty d507cd0c9a quartus optimization for frequency 2017-05-18 11:34:29 -04:00
Rejeesh Kutty ff7dc41066 alt-jesd- constraints update 2017-05-18 09:55:24 -04:00
Rejeesh Kutty d10faabc3f a10soc- 16.1- hsp sdram reset 2017-05-17 16:30:37 -04:00
Rejeesh Kutty f8f7bdd6a6 a10soc- fix version check 2017-05-17 16:26:28 -04:00
AndreiGrozav 70e3dd00ff scripts: Update required tool versions 2017-05-17 16:45:20 +03:00
Istvan Csomortani 9055774795 all: Update license for all hdl source files
All the hdl (verilog and vhdl) source files were updated. If a file did not
have any license, it was added into it. Files, which were generated by
a tool (like Matlab) or were took over from other source (like opencores.org),
were unchanged.

New license looks as follows:

Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.

Each core or library found in this collection may have its own licensing terms.
The user should keep this in in mind while exploring these cores.

Redistribution and use in source and binary forms,
with or without modification of this file, are permitted under the terms of either
 (at the option of the user):

  1. The GNU General Public License version 2 as published by the
     Free Software Foundation, which can be found in the top level directory, or at:
https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html

OR

  2.  An ADI specific BSD license as noted in the top level directory, or on-line at:
https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
2017-05-17 11:52:08 +03:00
Rejeesh Kutty c4b4bdc415 daq2/a10gx- constraints remove 16.0 2017-05-16 10:09:42 -04:00
Rejeesh Kutty cfcb269d38 a10gx- change ddr to 1G 2017-05-15 09:32:36 -04:00
Rejeesh Kutty 63b701ccab altera- add version check 2017-05-12 15:13:29 -04:00
Rejeesh Kutty ebeebdddf0 altera- infer latest versions 2017-05-12 13:40:14 -04:00
Rejeesh Kutty c728299e71 altera- default to latest version 2017-05-12 13:25:17 -04:00
Rejeesh Kutty ecfa15bfce version check- change to critical warning 2017-05-12 09:51:48 -04:00
Rejeesh Kutty 039ae9ae92 fmcadc5- syntax/port name fixes 2017-05-10 16:30:15 -04:00
Rejeesh Kutty 6a0a2e4661 hdlmake.pl updates 2017-05-10 14:35:06 -04:00
Rejeesh Kutty 74c44cf830 axi_fmcadc5- remove pack-driver is too late 2017-05-10 14:33:56 -04:00
Rejeesh Kutty 0e5a24ee7c axi_fmcadc5_sync- raw inputs & constraint fixes 2017-05-08 10:30:51 -04:00
Istvan Csomortani 6387b53266 ad77681evb: Initial commit 2017-05-04 12:19:11 +03:00
Istvan Csomortani ef97c1e375 adrv9371x/a10soc: Fix constraints
Signed-off-by: Istvan Csomortani <istvan.csomortani@analog.com>
2017-05-02 14:37:11 +03:00
AndreiGrozav f0bc3e20ef zcu102: Automatic IP version update fix 2017-05-02 12:52:43 +03:00
AndreiGrozav cd8f4f23be zcu102: Automatic IP version update 2017-05-02 12:30:00 +03:00
AndreiGrozav d6b09602ed usrpe31x: Automatic IP version update 2017-05-02 12:27:57 +03:00
AndreiGrozav 485c810c2c pzsdr*: Automatic IP version update 2017-05-02 11:43:32 +03:00
Rejeesh Kutty b3ce821311 change pl ddr clock to 1G 2017-05-01 09:35:10 -04:00
Rejeesh Kutty d29f420ffa axi_fmcadc5_sync: add a calibration signal generation 2017-04-28 11:13:24 -04:00
Lars-Peter Clausen 7a53b99b8b daq2: zc706: Increase DAC FIFO size
Currently the DAC FIFO size for the ZC706 DAQ2 project is 16kB. This is
quite a limiting size for practical applications. Increase the size to 1MB
to allow loading larger waveforms.

In this configuration the DAC FIFO will use half of the available BRAM
cells in the FPGA. This still leaves quite a few BRAMs available for
user application logic added to the design. If a user design should run out
of BRAMs nevertheless they can reduce the FIFO size, if not required by the
application, to free up some cells.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-28 12:29:01 +02:00
Istvan Csomortani f6eea23f5e adaq7980: Update tcl command for IP configuration 2017-04-28 10:12:33 +03:00
Istvan Csomortani 353d1d44da ad5766_sdz: Update tcl commands for IP configuration 2017-04-28 10:12:05 +03:00
Rejeesh Kutty 956753ca9c hdlmake- updates 2017-04-27 15:11:01 -04:00
Rejeesh Kutty 68fc5c89a7 fmcadc5- remove stand alone psync 2017-04-27 15:09:56 -04:00
Rejeesh Kutty 75c7525c60 fmcadc5- remove psync module 2017-04-27 13:29:06 -04:00
Rejeesh Kutty 2027c8427c adi_boadr- disconnect and remove unused ports 2017-04-27 13:26:17 -04:00
Rejeesh Kutty 902eaaaf4c fmcadc5- sync updates 2017-04-27 13:26:17 -04:00
Istvan Csomortani 0442e7d404 util_adxcvr: Fix parameter setup at instantiation
If a parameter value is defined as a string binary (e.g. "001001000000"),
it can confuse the tool, and the value may be used as a decimal number.
To prevent this issue and to improve readability converting all the binary
constants into hexadecimal.
2017-04-27 15:35:39 +03:00
Istvan Csomortani 8aa8d3a0e5 ad5766_sdz/zed: Fix i_iobuf_reset width 2017-04-27 11:28:26 +03:00
Istvan Csomortani 4836aa2179 adaq7980/zed: Update Makefile 2017-04-27 11:28:25 +03:00
Istvan Csomortani fbccb377cc adaq7980: Add an trigger generator for SPI offload 2017-04-27 11:28:23 +03:00
Istvan Csomortani 63cab50872 adaq7980_sdz: Initial commit
The device is interfaced with a SPI Engine, the PD lines are controlled
by GPIOs.
2017-04-27 11:28:23 +03:00
Dragos Bogdan ccc4aac505 ad5766_sdz: Fix the PIN assignment 2017-04-27 11:27:34 +03:00
Istvan Csomortani 8213d8a916 cn0363: Update block design
Configure the interconnect and offload modules inorder to activate
its interfaces. In the past, these interfaces did not have any
parameter dependencies, so this configuration were not required.
2017-04-27 11:27:33 +03:00
Istvan Csomortani a6146393be ad5766_sdz: Fix DMA data path 2017-04-27 11:22:32 +03:00