74b922f9f8
axi_*: Infer clock and reset signals of an IP
...
A clock sink must be connected to clock source, and a reset sink to
reset source, otherwise the tool will throw a synthesis warning.
By properly inferring all the reset and clock signals of an IP, we can
get rid of unwanted warning messages.
The following IPs tcl script was updated:
- axi_ad9434
- axi_hdmi_tx
- util_cpack
- util_adxcvr
- axi_ad6676
- axi_ad9625
- axi_ad9379
- axi_ad9265
- util_tdd_sync
- util_rfifo
- util_wfifo
- axi_ad9361
- axi_ad9467
- util_upack
- axi_dacfifo
- axi_ad9152
- axi_ad9680
- util_clkdiv
- axi_ad9122
- axi_ad9684
- axi_mc_speed
- axi_mc_current_monitor
- axi_mc_controller
- util_gmii_to_rgmii
- util_adxcvr
- axi_ad9379
- axi_hdmi
- library
- axi_fmcadc5_sync
- util_adcfifo
- util_mfifo
- axi_jesd204_rx
- axi_jesd204_tx
- axi_ad9361
- axi_adxcvr_ip
2018-04-11 15:09:54 +03:00
d3050abd3e
rfifo/upack- changes
2017-07-28 16:18:54 -04:00
c1bdfca4c3
library: Delete all adi_ip_constraint process call
2017-04-06 12:36:47 +03:00
e0efbe210e
constraints: constraint files should be specified at adi_ip_files
2017-04-03 18:12:28 +03:00
58a2a3259c
util_rfifo: updates
2016-05-16 12:19:38 -04:00
6862655b0d
Add .gitattributes file
...
Add .gitattributes file which sets up the eol encoding handling. This will
make sure that we get a uniform eol encoding across different operating
systems.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 11:07:10 +02:00
5f93c859b5
util_rfifo: renamed ports to make vivado happy
2015-01-06 16:16:42 -05:00
f9dfd944c9
library/util_fifo: updates for read side
2014-03-10 14:48:14 -04:00
d6256e9e29
library: dds and dcfilter changes, added fifo wrappers
2014-03-10 11:11:16 -04:00
Adrian Costina
Rejeesh Kutty
Istvan Csomortani
Lars-Peter Clausen