28eb09b4d5
axi-jesd-xcvr- parameter changes
2015-08-19 14:55:08 -04:00
928ee4972b
dac/adc-rst: common ad-rst instance
2015-08-19 14:54:43 -04:00
483e375910
dac/adc-rst: common ad-rst instance
2015-08-19 14:54:38 -04:00
5e252f17b9
cpack- ad_rst port addition
2015-08-19 13:26:38 -04:00
f8b3346e97
axi_jesd_xcvr- ad_rst register changes
2015-08-19 13:26:38 -04:00
f7f902c7b4
axi_jesd_xcvr- ad_rst register changes
2015-08-19 13:26:38 -04:00
57cfb7cfb1
hdl/library: Update the IP parameters
...
The following IP parameters were renamed:
PCORE_ID --> ID
PCORE_DEVTYPE --> DEVICE_TYPE
PCORE_IODELAY_GROUP --> IO_DELAY_GROUP
CH_DW --> CHANNEL_DATA_WIDTH
CH_CNT --> NUM_OF_CHANNELS
PCORE_BUFTYPE --> DEVICE_TYPE
PCORE_ADC_DP_DISABLE --> ADC_DATAPATH_DISABLE
CHID --> CHANNEL_ID
PCORE_DEVICE_TYPE --> DEVICE_TYPE
PCORE_MMCM_BUFIO_N --> MMCM_BUFIO_N
PCORE_SERDES_DDR_N --> SERDES_DDR_N
PCORE_DAC_DP_DISABLE --> DAC_DATAPATH_DISABLE
DP_DISABLE --> DATAPATH_DISABLE
PCORE_DAC_IODELAY_ENABLE --> DAC_IODELAY_ENABLE
C_BIG_ENDIAN --> BIG_ENDIAN
C_M_DATA_WIDTH --> MASTER_DATA_WIDTH
C_S_DATA_WIDTH --> SLAVE_DATA_WIDTH
NUM_CHANNELS --> NUM_OF_CHANNELS
CHANNELS --> NUM_OF_CHANNELS
PCORE_4L_2L_N -->QUAD_OR_DUAL_N
C_ADDRESS_WIDTH --> ADDRESS_WIDTH
C_DATA_WIDTH --> DATA_WIDTH
C_CLKS_ASYNC --> CLKS_ASYNC
PCORE_QUAD_DUAL_N --> QUAD_DUAL_N
NUM_CS --> NUM_OF_CS
PCORE_DAC_CHANNEL_ID --> DAC_CHANNEL_ID
PCORE_ADC_CHANNEL_ID --> ADC_CHANNEL_ID
PCORE_CLK0_DIV --> CLK0_DIV
PCORE_CLK1_DIV --> CLK1_DIV
PCORE_CLKIN_PERIOD --> CLKIN_PERIOD
PCORE_VCO_DIV --> VCO_DIV
PCORE_Cr_Cb_N --> CR_CB_N
PCORE_VCO_MUL --> VCO_MUL
PCORE_EMBEDDED_SYNC --> EMBEDDED_SYNC
PCORE_AXI_ID_WIDTH --> AXI_ID_WIDTH
PCORE_ADDR_WIDTH --> ADDRESS_WIDTH
DADATA_WIDTH --> DATA_WIDTH
NUM_OF_NUM_OF_CHANNEL --> NUM_OF_CHANNELS
DEBOUNCER_LEN --> DEBOUNCER_LENGTH
ADDR_WIDTH --> ADDRESS_WIDTH
C_S_AXIS_REGISTERED --> S_AXIS_REGISTERED
Cr_Cb_N --> CR_CB_N
ADDATA_WIDTH --> ADC_DATA_WIDTH
BUFTYPE --> DEVICE_TYPE
NUM_BITS --> NUM_OF_BITS
WIDTH_A --> A_DATA_WIDTH
WIDTH_B --> B_DATA_WIDTH
CH_OCNT --> NUM_OF_CHANNELS_O
M_CNT --> NUM_OF_CHANNELS_M
P_CNT --> NUM_OF_CHANNELS_P
CH_ICNT --> NUM_OF_CHANNELS_I
CH_MCNT --> NUM_OF_CHANNELS_M
4L_2L_N --> QUAD_OR_DUAL_N
SPI_CLK_ASYNC --> ASYNC_SPI_CLK
MMCM_BUFIO_N --> MMCM_OR_BUFIO_N
SERDES_DDR_N --> SERDES_OR_DDR_N
CLK_ASYNC --> ASYNC_CLK
CLKS_ASYNC --> ASYNC_CLK
SERDES --> SERDES_OR_DDR_N
GTH_GTX_N --> GTH_OR_GTX_N
IF_TYPE --> DDR_OR_SDR_N
PARALLEL_WIDTH --> DATA_WIDTH
ADD_SUB --> ADD_OR_SUB_N
A_WIDTH --> A_DATA_WIDTH
CONST_VALUE --> B_DATA_VALUE
IO_BASEADDR --> BASE_ADDRESS
IO_WIDTH --> DATA_WIDTH
QUAD_DUAL_N --> QUAD_OR_DUAL_N
AXI_ADDRLIMIT --> AXI_ADDRESS_LIMIT
ADDRESS_A_DATA_WIDTH --> A_ADDRESS_WIDTH
ADDRESS_B_DATA_WIDTH --> B_ADDRESS_WIDTH
MODE_OF_ENABLE --> CONTROL_TYPE
CONTROL_TYPE --> LEVEL_OR_PULSE_N
IQSEL --> Q_OR_I_N
MMCM --> MMCM_OR_BUFR_N
2015-08-19 14:11:47 +03:00
549801cf2e
library: Delete unused IP cores
...
Delete IP "controllerperipheralhdladi_pcore" and "ip_pid_controller"
2015-08-19 12:24:10 +03:00
10d9de39a1
axi_ad9361/tdd: Update the synchronization logic
...
The master will regenerate a sync pulse periodically. The period can be defined by software.
2015-08-19 12:21:23 +03:00
bcee3e04d4
fmcomms2_tdd: Update tdd_enabaled path
...
This line controls the mux, which switch between hdl and software (GPIO) control of the ENABLE/TXNRX pins.
Fix the broken path and change the name from "tdd_enable" to "tdd_enabled".
2015-08-19 12:14:05 +03:00
8e536ad8d1
axi_ad9361: Update Make file
2015-08-19 12:14:03 +03:00
e64baad54a
axi_dmac: Fix a bug occuring on transfers < one beat
...
Signed-off-by: Paul Cercueil <paul.cercueil@analog.com>
2015-08-19 10:23:26 +02:00
b84afcdcd1
Merge branch 'master' into dev
...
Conflicts:
library/Makefile
library/axi_ad6676/axi_ad6676_ip.tcl
library/axi_ad9122/axi_ad9122_core.v
library/axi_ad9122/axi_ad9122_ip.tcl
library/axi_ad9144/axi_ad9144_ip.tcl
library/axi_ad9152/axi_ad9152_ip.tcl
library/axi_ad9234/axi_ad9234_ip.tcl
library/axi_ad9250/axi_ad9250_hw.tcl
library/axi_ad9250/axi_ad9250_ip.tcl
library/axi_ad9361/axi_ad9361.v
library/axi_ad9361/axi_ad9361_dev_if_alt.v
library/axi_ad9361/axi_ad9361_ip.tcl
library/axi_ad9361/axi_ad9361_rx_channel.v
library/axi_ad9361/axi_ad9361_tdd.v
library/axi_ad9361/axi_ad9361_tx_channel.v
library/axi_ad9625/axi_ad9625_ip.tcl
library/axi_ad9643/axi_ad9643_channel.v
library/axi_ad9643/axi_ad9643_ip.tcl
library/axi_ad9652/axi_ad9652_channel.v
library/axi_ad9652/axi_ad9652_ip.tcl
library/axi_ad9671/axi_ad9671_constr.xdc
library/axi_ad9671/axi_ad9671_ip.tcl
library/axi_ad9680/axi_ad9680_ip.tcl
library/axi_ad9739a/axi_ad9739a_ip.tcl
library/axi_dmac/axi_dmac_constr.sdc
library/axi_hdmi_tx/axi_hdmi_tx_ip.tcl
library/axi_jesd_gt/axi_jesd_gt_constr.xdc
library/axi_jesd_gt/axi_jesd_gt_ip.tcl
library/axi_mc_speed/axi_mc_speed_constr.xdc
library/common/ad_gt_channel_1.v
library/common/ad_gt_common_1.v
library/common/ad_gt_es.v
library/common/ad_iqcor.v
library/common/ad_jesd_align.v
library/common/ad_rst.v
library/common/altera/ad_xcvr_rx_rst.v
library/common/up_adc_common.v
library/common/up_axis_dma_rx.v
library/common/up_axis_dma_tx.v
library/common/up_clkgen.v
library/common/up_clock_mon.v
library/common/up_dac_common.v
library/common/up_gt.v
library/common/up_hdmi_tx.v
library/common/up_tdd_cntrl.v
library/common/up_xfer_cntrl.v
library/common/up_xfer_status.v
library/util_cpack/util_cpack.v
library/util_cpack/util_cpack_ip.tcl
library/util_dac_unpack/util_dac_unpack_hw.tcl
library/util_jesd_align/util_jesd_align.v
library/util_jesd_xmit/util_jesd_xmit.v
library/util_upack/util_upack_ip.tcl
library/util_wfifo/util_wfifo.v
library/util_wfifo/util_wfifo_constr.xdc
library/util_wfifo/util_wfifo_ip.tcl
projects/arradio/c5soc/system_bd.qsys
projects/common/vc707/vc707_system_bd.tcl
projects/common/zc706/zc706_system_plddr3.tcl
projects/daq2/a10gx/Makefile
projects/daq2/a10gx/system_bd.qsys
projects/daq3/common/daq3_bd.tcl
projects/daq3/zc706/system_bd.tcl
projects/fmcjesdadc1/a5gt/Makefile
projects/fmcjesdadc1/a5gt/system_bd.qsys
projects/fmcjesdadc1/a5gt/system_constr.sdc
projects/fmcjesdadc1/a5gt/system_top.v
projects/fmcjesdadc1/a5soc/system_bd.qsys
projects/fmcjesdadc1/common/fmcjesdadc1_bd.tcl
projects/fmcomms1/ac701/system_bd.tcl
projects/fmcomms1/common/fmcomms1_bd.tcl
projects/fmcomms1/kc705/system_bd.tcl
projects/fmcomms1/vc707/system_bd.tcl
projects/fmcomms1/zc702/system_bd.tcl
projects/fmcomms1/zc702/system_top.v
projects/fmcomms1/zc706/system_bd.tcl
projects/fmcomms1/zc706/system_top.v
projects/fmcomms1/zed/system_bd.tcl
projects/fmcomms1/zed/system_top.v
projects/fmcomms2/ac701/system_constr.xdc
projects/fmcomms2/common/fmcomms2_bd.tcl
projects/fmcomms2/kc705/system_constr.xdc
projects/fmcomms2/kc705/system_top.v
projects/fmcomms2/mitx045/system_top.v
projects/fmcomms2/rfsom/system_constr.xdc
projects/fmcomms2/rfsom/system_top.v
projects/fmcomms2/vc707/system_top.v
projects/fmcomms2/zc706/system_bd.tcl
projects/fmcomms2/zc706/system_constr.xdc
projects/fmcomms2/zc706/system_top.v
projects/fmcomms2/zed/system_top.v
projects/imageon/zc706/system_constr.xdc
projects/motcon2_fmc/common/motcon2_fmc_bd.tcl
projects/motcon2_fmc/zed/system_constr.xdc
projects/motcon2_fmc/zed/system_top.v
projects/usdrx1/a5gt/Makefile
projects/usdrx1/a5gt/system_bd.qsys
projects/usdrx1/common/usdrx1_bd.tcl
Conflicts were resolved using 'Mine' (/dev).
2015-08-17 15:15:58 +03:00
c22d1c044b
axi_jesd_gt-- gt interfaces
2015-08-14 15:34:49 -04:00
890f743f1a
util_jesd_gt-- gt interfaces
2015-08-14 15:34:30 -04:00
6eb0b5eeda
scripts-- add interface procedures
2015-08-14 15:33:58 -04:00
2345be2237
interfaces-- transceiver cores
2015-08-14 15:33:36 -04:00
af87b65788
interfaces_ip: added
2015-08-14 11:24:27 -04:00
ebecfde64c
axi_hdmi_tx: common constraints & async resets
2015-08-13 13:03:51 -04:00
a6f6c81795
axi_jesd_gt- gt lane split
2015-08-13 13:03:51 -04:00
041be729f6
common/ip-constrs- uniform simple constraints will do
2015-08-13 13:03:51 -04:00
a2b816beda
common/up_hdmi_tx: wrong clock on vdma status signals
2015-08-13 13:03:51 -04:00
5edf61c40a
ad_rst:- allow preset to be synchronized as reset
2015-08-13 13:03:51 -04:00
2bcac36e33
common/up_- change to asynchronous resets
2015-08-13 13:03:51 -04:00
2b8e1bdb74
adi_ip- parse file list for constraints
2015-08-13 13:03:51 -04:00
3615c9cad7
axi_jesd_gt- bug fixes
2015-08-13 13:03:51 -04:00
44d51e665d
util_jesd_gt- port type fix
2015-08-13 13:03:51 -04:00
8697b0a8d6
axi_jesd_gt- ip script changes
2015-08-13 13:03:51 -04:00
e265ca9ea7
util_jesd_gt- ip tcl changes
2015-08-13 13:03:51 -04:00
a108ca9309
util_jesd_gt- updates
2015-08-13 13:03:51 -04:00
a4076424e0
util_jesd_gt- added
2015-08-13 13:03:51 -04:00
10d4da64dd
axi_jesd_gt: move master/slave control to a util module
2015-08-13 13:03:51 -04:00
3ed350efbc
axi_jesd_gt- split up
2015-08-13 13:03:51 -04:00
e4f94664a6
axi_jesd_gt- remove per lane control/status to channel
2015-08-13 13:03:51 -04:00
f807490ed1
axi_jesd_gt- per lane group
2015-08-13 13:03:51 -04:00
4c8206608c
axi_jesd_gt- separate es-axi
2015-08-13 13:03:51 -04:00
e4b0710923
axi_jesd_gt- per lane split-up
2015-08-13 13:03:51 -04:00
ce26373e8a
axi_ad9671: updated constraints to apply in all cases
2015-08-13 11:53:15 +03:00
0379279bd4
axi_ad9671: Fixed rx_sof pin name
2015-08-12 10:20:09 +03:00
afb9911b6e
Makefiles: Updated makefiles
2015-08-06 19:50:50 +03:00
f59058dd8a
axi_ad9434: Fix the up interface for IO_DELAYs
2015-08-06 15:17:19 +03:00
ad80561379
TDD_regmap: Fix CDC for control signals
2015-08-06 15:16:39 +03:00
e19d476b58
TDD_regmap: Fix addresses
2015-08-06 15:15:50 +03:00
d2c99acae8
fmcomms2/TDD: Update synchronization interface
...
Synchronization is done by a simple req/ack interface between a master and slave terminal.
2015-08-06 15:14:36 +03:00
6104061d19
axi_ad9434: Fix the up interface for IO_DELAYs
2015-08-04 13:46:15 +03:00
cfc4046821
fmcomms2: Add a synchronization interface for TDD mode.
...
Supported carrier are ZC706 and RFSOM.
The synchronization pulse is automatically generated by the master terminal, when TDD mode is enabled.
By default a terminal is slave, software must write 0x01 into TDD register 0x50.
2015-07-29 14:10:56 +03:00
ed6bdf66bd
axi_ad9361/tdd: Add new control signals to the TDD data flow control logic
...
Add tdd_gated_[tx/rx]_dmapath control bits to the TDD logic. With these control line, the user can choose between gated and free-running (like in FDD mode) data flow control.
2015-07-29 11:59:17 +03:00
05ba125694
ad_tdd_control: Connect the reset to all the flops
2015-07-29 11:56:40 +03:00
8e631e56d6
fmcomms2: Add a synchronization interface for TDD mode.
...
Supported carrier are ZC706 and RFSOM.
The synchronization pulse is automatically generated by the master terminal, when TDD mode is enabled.
By default a terminal is slave, software must write 0x01 into TDD register 0x50.
2015-07-28 14:42:54 +03:00
d5d7a24483
util_cpack: Added reset interface
2015-07-28 11:00:54 +03:00
623c3dc333
axi_ad9361: Updated altera core by including tdd related files. Removed deleted ports
2015-07-24 16:41:41 +03:00
caca364c61
ad9652- iqcor iqsel changes
2015-07-24 08:35:13 -04:00
144b8f7383
ad9643- iqcor iqsel changes
2015-07-24 08:34:52 -04:00
43946a54a4
axi_dmac: Added C_FIFO_SIZE parameter
2015-07-24 15:30:10 +03:00
649297a0e3
ad_iqcor- changes
2015-07-23 16:20:46 -04:00
cd5ce3349f
iqcor- move i/q sel inside the module
2015-07-23 15:55:45 -04:00
3d1ffe7bd2
util_cpack: Added reset interface
2015-07-23 17:01:53 +03:00
f7d28e0944
axi_dmac: Removed unneded constraints, as FMCJESDADC1 doesn't work correctly with them
2015-07-23 17:01:02 +03:00
41e9a34886
axi_ad9250: Changed Altera interface specification to be compatible with upack
2015-07-23 16:59:57 +03:00
901bcb2c06
dma- constraints modifications
2015-07-22 12:46:06 -04:00
3d7afb8fc5
jesd-xcvr: constraints modifications
2015-07-22 12:46:06 -04:00
6352884398
jesd-xcvr: common align function
2015-07-22 12:46:06 -04:00
a4461545fa
axi-ip: constraints - altera
2015-07-22 12:46:06 -04:00
ac39329046
axi_spdif_rx: Fix the pl330_dma control path
...
- fix pl330_dma control path
- delete unused control_reg bits
- change the port name spdif_rx_i_osc to spdif_rx_i_dbg
- version_reg is read only
2015-07-22 17:59:52 +03:00
559893c0a3
altera- obsolete cores
2015-07-21 11:04:26 -04:00
86dabbe5fc
jesd-align-- xilinx/altera merge
2015-07-21 10:57:00 -04:00
3a4581a8df
axi-xcvr: removed xcvr compoents
2015-07-21 10:56:04 -04:00
264f9ffbfc
ip_alt- avalon/reset definitions
2015-07-21 10:55:13 -04:00
3101045109
qsys- library group
2015-07-17 10:07:15 -04:00
4e99a2cb01
xcvr: remove signal tap
2015-07-16 08:09:56 -04:00
9f7fff2d2f
axi_ad9361/tdd: Add new control signals to the TDD data flow control logic
...
Add tdd_gated_[tx/rx]_dmapath control bits to the TDD logic. With these control line, the user can choose between gated and free-running (like in FDD mode) data flow control.
2015-07-16 14:10:49 +03:00
31584cf27e
ad9680- qsys needs interface signal name matching
2015-07-15 15:59:51 -04:00
60c344cea6
ad9144- qsys needs interface signal name matching
2015-07-15 15:59:51 -04:00
29c6e90d38
util_bsplit: remove avalon streaming interface
2015-07-15 09:44:57 -04:00
af898de818
axi_jesd_xcvr: remove avalon streaming interface
2015-07-15 09:44:56 -04:00
ea57e49da7
axi_ad9250: remove avalon streaming interface
2015-07-15 09:44:54 -04:00
6e3817d419
axi_jesd_xcvr: individual reset control
2015-07-13 10:04:34 -04:00
8d6c39d307
ad9680- remove avalon streaming
2015-07-13 10:03:38 -04:00
c69e36314c
ad9144- remove avalon streaming
2015-07-13 10:03:16 -04:00
9d95ddc620
reset and clock additions
2015-07-09 14:29:08 -04:00
d6d263341e
signal tap needs another method
2015-07-08 15:47:47 -04:00
b25b2e3020
registers for signal tap
2015-07-08 15:47:45 -04:00
c972779217
motcon2_fmc: updated util_gmii_to_rgmii and motcon2_fmc project for improved performance of the ethernet
...
- removed the delay controller from the top file and added it inside the util_gmii_to_rgmii core
- removed delay related xdc constraints as they are not needed
2015-07-08 16:23:33 +03:00
b4eb7465ed
library: Add missing Makefiles for axi_spdif_rx, util_jesd_align, util_jesd_xmit
2015-07-08 10:48:58 +03:00
23428ac48b
transceiver constraints for sysref
2015-07-07 15:25:36 -04:00
ea2bd71904
synchronize up signals separately
2015-07-07 12:51:13 -04:00
c1fcbeec8e
library/axi_jesd_xcvr: interface name matching
2015-07-07 10:21:53 -04:00
b106b8a8f4
library/axi_jesd_xcvr: updates
2015-07-06 13:51:55 -04:00
c67ca682a4
hw.tcl- added
2015-07-06 13:51:55 -04:00
1cfe6fe792
axi_jesd_xcvr: initial commit
2015-07-06 13:51:55 -04:00
3a5da47239
xcvr- initial checkin
2015-07-06 13:51:55 -04:00
46fa91d5be
Makefile: Update Make files
2015-07-03 18:08:57 +03:00
7376218e01
axi_spdif_rx: Initial commit
...
NOT tested.
2015-07-03 17:46:45 +03:00
896888d495
axi_mc_current_monitor: updated ad7401 driver to send unsigned data
2015-07-02 14:23:19 +03:00
04527f8b18
axi_mc_current_monitor: updated ad7401 driver to send unsigned data
2015-07-02 14:21:26 +03:00
3c6d19d33d
axi_hdmi_tx_es: Drop strange port initializers
...
Those were added by mistake. It does not seem to be legal Verilog, but for
some reason Vivado accepts it.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-07-01 18:43:51 +02:00
26b0ff9853
axi_hdmi_tx: Don't accidentally send control characters in embedded sync mode
...
ffff and 0000 are always reserved control characters when using embedded
syncs. So make sure that we never have them in the pixel data, even when
running in full-range mode.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-07-01 18:43:51 +02:00
6aee17da83
axi_hdmi_tx: Add control to bypass chroma sub-sampler
...
Add a control bit to the register map that allows to bypass the chroma
sub-sampler in the axi_hdmi_tx core. This is primarily interned to be used
to send the test-pattern directly to the HDMI transmitter without modifying
it.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-07-01 18:43:51 +02:00
35988b2dba
axi_hdmi_rx: Fix packed 422 mode
...
Currently the hdmi_de_int signal is asserted one clock cycle too early in
packed 422 mode. As a result the EAV sequence ends up in the first pixel
and every other pixel is off by one.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-07-01 18:43:51 +02:00
fa15f8d0b5
axi_hdmi_rx: Add full range support to the TPM
...
Check for both full range and limited range test-pattern sequences and only
if both don't match assert the tpm_oos signal.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-07-01 18:43:51 +02:00
fcb841d3e5
axi_hdmi_rx: Move TPM to its own module
...
Move the test pattern matcher to its own module. This makes it easier to
use it in other configurations as well.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-07-01 18:43:51 +02:00
ab6ea2c824
axi_hdmi_rx: Drop TPG enable from register map
...
The TPG is no longer part of the RX core and the corresponding bit in the
register map isn't hooked up to anything. So drop it.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-07-01 18:43:51 +02:00
a2a4f3402c
up_hdmi_rx: Fix TPM OOS clear
...
The TPM OOS status flag is in bit 1. Make sure writing to bit 1 rather than
bit 0 clears the TPM OOS.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-07-01 18:43:51 +02:00
c372064302
Add .gitattributes file
...
Add .gitattributes file which sets up the eol encoding handling. This will
make sure that we get a uniform eol encoding across different operating
systems.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-07-01 18:43:51 +02:00
4744fca18e
axi_ad9361: Bring up the tdd_enable bit
...
This line will be the selection bit of the GPIO/TDD_FSM mux for ENABLE/TXNRX control
2015-07-01 14:59:32 +03:00
a497dcabb5
axi_ad9361: Bring up the tdd_enable bit
...
This line will be the selection bit of the GPIO/TDD_FSM mux for ENABLE/TXNRX control
2015-07-01 13:52:00 +03:00
23034965c8
axi_hdmi_tx_es: Drop strange port initializers
...
Those were added by mistake. It does not seem to be legal Verilog, but for
some reason Vivado accepts it.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-30 21:16:09 +02:00
cb03152f1f
axi_hdmi_tx: Don't accidentally send control characters in embedded sync mode
...
ffff and 0000 are always reserved control characters when using embedded
syncs. So make sure that we never have them in the pixel data, even when
running in full-range mode.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-30 21:16:09 +02:00
cf6052e2a8
axi_hdmi_tx: Add control to bypass chroma sub-sampler
...
Add a control bit to the register map that allows to bypass the chroma
sub-sampler in the axi_hdmi_tx core. This is primarily interned to be used
to send the test-pattern directly to the HDMI transmitter without modifying
it.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-30 21:16:09 +02:00
bc4bb111d9
axi_hdmi_rx: Fix packed 422 mode
...
Currently the hdmi_de_int signal is asserted one clock cycle too early in
packed 422 mode. As a result the EAV sequence ends up in the first pixel
and every other pixel is off by one.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-30 18:02:44 +02:00
13c122f1a1
axi_hdmi_rx: Add full range support to the TPM
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Check for both full range and limited range test-pattern sequences and only
if both don't match assert the tpm_oos signal.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-30 18:02:43 +02:00
4503402eef
axi_hdmi_rx: Move TPM to its own module
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Move the test pattern matcher to its own module. This makes it easier to
use it in other configurations as well.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-30 18:02:43 +02:00
d6c64e031f
axi_hdmi_rx: Drop TPG enable from register map
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The TPG is no longer part of the RX core and the corresponding bit in the
register map isn't hooked up to anything. So drop it.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-30 18:02:43 +02:00
542d64bb5a
up_hdmi_rx: Fix enable control
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Connect the enable signal in the register map to the up_preset signal so
that it is possible to enable/disable to core at runtime.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-30 18:02:43 +02:00
231a21548c
up_hdmi_rx: Fix TPM OOS clear
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The TPM OOS status flag is in bit 1. Make sure writing to bit 1 rather than
bit 0 clears the TPM OOS.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-30 18:02:43 +02:00
185e489802
cpack- signaltap mess
2015-06-29 16:31:53 -04:00
caabb9444a
axi_mc_speed: Removed unneded constraints
2015-06-29 16:53:39 +03:00
6862655b0d
Add .gitattributes file
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Add .gitattributes file which sets up the eol encoding handling. This will
make sure that we get a uniform eol encoding across different operating
systems.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 11:07:10 +02:00
fcc185d769
Makefile: Updated makefiles
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- removed up_drp_control, up_delay_control dependencies where not needed
- added axi_jesd_gt core in the library makefile
- fixed timing tcl dependency for altera projects
2015-06-25 14:59:34 +03:00
c9d976d4f7
axi_hdmi_rx: Fix alignment issue on packed formats
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Some cases, when software changed the image formats, the packed formats (24bit/pixel) lost alignment.
(the first 32 bit after sof got lost) This commit fix that issue.
2015-06-24 12:47:15 +03:00
1abd1a46b1
axi_hdmi_rx: Fix synchronization issues
2015-06-24 12:47:02 +03:00
c0dd80ccee
axi_hdmi_rx: Fix alignment issue on packed formats
...
Some cases, when software changed the image formats, the packed formats (24bit/pixel) lost alignment.
(the first 32 bit after sof got lost) This commit fix that issue.
2015-06-24 12:43:55 +03:00
281a47c117
bsplit- altera version, avalon needs a clock
2015-06-24 05:31:08 -04:00
f4a1a5817c
jesd-align: allow sof pass through -- qsys can only do 1 src-dest
2015-06-24 05:31:06 -04:00
e1b1e1bc2c
ad9250- update to use alt ip interface script
2015-06-24 05:31:04 -04:00
00bc48bc24
axi_hdmi_rx: Fix synchronization issues
2015-06-24 11:03:39 +03:00
4e30a5b0bf
axi_ad9250: Updated altera core to work with axi4lite interface
2015-06-23 14:29:23 +03:00
c9e152e500
axi_ad9250: Updated altera core to work with axi4lite interface
2015-06-23 14:28:02 +03:00
3e5a5504a7
library/jesd-align- remove signaltap interface
2015-06-19 14:33:03 -04:00
af2ffbe0a0
library/cpack- add signaltap
2015-06-19 14:33:02 -04:00
ac6e28c461
library/common: add altera signaltap
2015-06-19 14:33:01 -04:00
8a52631189
libary: util_jesd_align- signal tap interface
2015-06-19 14:32:57 -04:00
7e08ff0422
library: added util_jesd_xmit
2015-06-19 14:32:56 -04:00
ad743c8403
axi_ad9434: This IP core does not have 'data underflow' port
2015-06-18 16:51:42 +03:00
d137811952
util_gmii_to_rgmii: Updated core so that it has an option to include a delay controller.
...
It also allows to configure the fixed delay value so that no additional constraints are needed
The default value of 18 seems to work very well(450mbps tx / 640 mbps rx) on the motor control platform used for tests
2015-06-16 17:39:31 +03:00
28e8275a5d
library/axi_jesd_gt: split gt lanes
2015-06-12 15:56:03 -04:00
ddc08c960c
ad_tdd_control: Connect the reset to all the flops
2015-06-11 12:07:47 +03:00
04eb998ff1
axi_jesd_gt: constraints
2015-06-10 14:29:06 -04:00
e2f4a4c5cf
library: make preset registered for timing paths
2015-06-10 13:41:41 -04:00
df0eaad1e2
gt: constraints
2015-06-10 11:38:15 -04:00
d6163bea5e
axi_jesd_gt: Fixed constraints
2015-06-10 10:56:22 +03:00
5e4f572092
axi_ad9122: Fixed constraints
2015-06-10 10:56:03 +03:00
8a1f4bf5f6
ad6676,ad9144,ad9152,ad9234,ad9250,ad9434,ad9467,ad9625,ad652,ad9671,ad9680,ad9739a:Set default driver value for overflow, underflow, gpio_in and dac_sync ports
2015-06-09 14:21:12 +03:00
a598e1c614
axi_ad9265: Set default driver value for overflow and underflow ports
2015-06-08 17:50:23 +03:00
ccf887f0ba
axi_ad9643: Set default driver values for overflow, underflow and gpio_in ports
2015-06-08 17:48:41 +03:00
ded0dd5dbe
axi_ad9122: fixed constraints, removed unneded drp reset
2015-06-08 17:45:14 +03:00
4b08df9ed6
ad9361/tdd: Fix generation of tx_valid_* signals
...
In FDD mode the tx_valid_* signals are generated inside the axi_ad9361_tx module, in function of
the selected dac data rate. In TDD mode, these signals are gated by the tdd_enable and tdd_tx_dp_en signals.
In other words, the tx_valid_* signals will be valid just when tdd_enable and tdd_tx_dp_en is active.
2015-06-08 16:23:32 +03:00
c926daca3a
ad9361/tdd: Fix generation of tx_valid_* signals
...
In FDD mode the tx_valid_* signals are generated inside the axi_ad9361_tx module, in function of
the selected dac data rate. In TDD mode, these signals are gated by the tdd_enable and tdd_tx_dp_en signals.
In other words, the tx_valid_* signals will be valid just when tdd_enable and tdd_tx_dp_en is active.
2015-06-08 16:22:21 +03:00
ce60056cd5
wfifo: async reset for cpu side
2015-06-05 12:44:04 -04:00
ab1f9bed10
wfifo: remove srl from sync registers
2015-06-05 12:44:04 -04:00
Rejeesh Kutty
Istvan Csomortani
Paul Cercueil
Adrian Costina
Lars-Peter Clausen