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4 Commits (3e0b337eaebe1dbd4a0665d04c71f467231b1eb8)

Author SHA1 Message Date
Istvan Csomortani c1bdfca4c3 library: Delete all adi_ip_constraint process call 2017-04-06 12:36:47 +03:00
Adrian Costina 1c8e63cb68 axi_adc_trigger: Added triggered register 2017-02-27 14:26:19 +02:00
Istvan Csomortani ac2e5a9dac constraints: Update constraints 
Xilinx recommends that all synchronizer flip-flops have
their ASYNC_REG property set to true in order to preserve the
synchronizer cells through any logic optimization during synthesis
and implementation.
 2017-02-24 13:43:32 +02:00
Adrian Costina 35b97abc6d axi_adc_trigger: Initial commit 2017-01-31 16:20:13 +02:00