3e565bc03c
fmcadc5: Disable constraints for jesd sysref in order to remove critical warning
2017-11-24 14:48:38 +02:00
ec324652aa
daq2_zcu102: Fix typo
2017-11-20 18:02:22 +02:00
a23c640180
Require Vivado 2017.2.1 for all zcu102 projects
2017-11-20 15:36:51 +00:00
f1e51a8b89
adrv9371x_zcu102: Fix rx_div_clk constraint placement
2017-11-20 15:36:51 +00:00
7759bfdf96
fmcadc5: Update make
2017-11-20 15:16:30 +02:00
c07fefcbd7
fmcadc5: Update to the ADI JESD interface
2017-11-20 15:12:47 +02:00
b54dab33e0
Make: Update makefiles
2017-11-20 14:27:39 +02:00
76cec098d1
daq2, daq3: zcu102: Update constraints
...
Differential pins ignored by the tool
2017-11-15 10:47:01 +02:00
8fa50a0cb4
daq2: Set correct transceiver type for UltraScale projects
...
Make sure that the axi_adxcvr instances are configured with the same
transceiver type as the util_adxcvr.
This is necessary for software to be able to detect the transceiver type
and support dynamic reconfiguration.
It is also necessary for correct eye scan support in the axi_adxcvr block.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-11-14 14:31:03 +01:00
46acdadb92
adrv9371x: Set correct transceiver type for UltraScale projects
...
Make sure that the axi_adxcvr instances are configured with the same
transceiver type as the util_adxcvr.
This is necessary for software to be able to detect the transceiver type
and support dynamic reconfiguration.
It is also necessary for correct eye scan support in the axi_adxcvr block.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-11-14 14:31:03 +01:00
caac2ce588
adrv9371x: zcu102: Fix lane mapping
...
Fix the location assignment of the transceiver blocks to get the correct
lane mapping.
Note that the comments indicating the expected lane mapping are correct,
but the actual transceiver location assignments were not.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-11-14 14:31:03 +01:00
f181e037cc
adrv9371x: zcu102: Fix QPLL feedback divider
...
The external reference clock runs at 122.88 MHz by default. This means that
the QPLL feedback divider needs to be set to 80 so that the VCO is inside
the locking range (9.8 GHz - 16.375 GHz).
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-11-14 14:31:03 +01:00
45f2fbf3c0
fmcjesdadc1: Update A10GX/A10SOC projects to the ADI JESD framework
2017-11-08 14:35:18 +02:00
514e54287c
zcu102 constraints description/cosmetic updates
2017-11-08 10:38:39 +02:00
22808fa03c
zcu102: Update to rev 1.0
2017-11-08 10:33:12 +02:00
7062785947
fmcomms2: Connect dac data underflow
...
DAC data underflow from the DMA, was not connected to anything. This
signal should be connected to the util_rfifo, which will forward it to
the device core.
2017-11-06 10:29:34 +00:00
f692d7bc40
daq3: Disable start synchronization for the ADC DMA
...
The ADC FIFO does not provide any sync output and for two channels it's not needed
2017-11-01 09:31:19 +02:00
2b4b9d7bab
daq2: Disable start synchronization for the ADC DMA
2017-10-31 17:16:08 +02:00
e3ea51ade3
avl_dacfifo: Refactor the fifo
...
+ Build both the read and write logic around an FSM
+ Consistent naming of registers and wires
+ Add support for burst lenghts higher than one, current burst lenght
is 64
+ Fix all the bugs, and make it work (first bring up with
adrv9371x/a10soc)
2017-10-31 14:30:06 +00:00
5b9e4cb692
daq2/zcu102: Pin Swap for ZCU102 Rev1.0
...
Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
2017-10-30 11:09:20 +00:00
22df03f9a4
daq3: A10GX, overconstrained failing paths
2017-10-28 08:21:50 +01:00
fe1adb6e4f
daq3: A10GX, updated to the ADI JESD204
...
- changed lane rate to 12.33Gbps
- added dac fifo
2017-10-25 14:45:27 +01:00
de5a21af80
daq2: A10GX, added additional interconnect pipelining
2017-10-23 16:39:58 +01:00
e8bab0b45f
adi_env: Normalize environment variables
...
If the ADI_HDL_DIR or ADI_PHDL_DIR are set on Windows platforms, an
invalid TCL character (e.g. backslash) may be used as a file separator,
causing issues with the build / library scripts.
Normalize the paths before using them as global TCL variables.
2017-10-23 12:15:14 +01:00
37323e3444
adrv9371x: A10GX, added extra pipelining in the interconnect in order to improve timing
2017-10-20 13:46:22 +01:00
aa6af4e522
daq2: A10GX, added extra pipelining in the interconnect in order to improve timing
2017-10-20 13:45:05 +01:00
083962450a
daq2: A10GX, connect dac_fifo_bypass to gpio
2017-10-19 16:07:18 +03:00
e43056455c
daq2: A10SOC, added dac fifo
2017-10-12 14:16:05 +03:00
72d9c1c6f2
daq2: A10GX, added dac fifo
2017-10-11 12:52:15 +03:00
d9acdb8092
usdrx1/a10gx: Add external flash support
2017-10-06 08:47:24 +01:00
baf8ec09a3
fmcjesdadc1/a10gx: Add external flash support
2017-10-06 08:46:22 +01:00
df70a6605c
daq3/a10gx: Add external falsh support
2017-10-06 08:45:33 +01:00
be4e02aed9
adrv9371x/a10gx: Add external flash support
2017-10-06 08:43:58 +01:00
d690a614c1
a10gx: Force all used tiles to high speed, in order to improve timing
2017-10-04 16:16:00 +01:00
03e744f0f1
daq1_zed: Lower the adc and daq clock to 450MHz
...
The FPGA fabric on zedboard is a -1 speadgrade (max bufg clk 464MHz)
2017-10-04 13:01:14 +01:00
7a3c4ab81f
arradio: Changed ADC DMA buswidth connection to the DDR to 128 bits
...
This fixes the bandwidth issue when data is streamed from the DDR and the system works at 61.44 MSPS
2017-10-04 13:01:14 +01:00
ee01ea3736
daq2/a10gx: Add cfi_flash to qsys
...
+ Add cfi_flash to qsys
+ Set nios reset vector to cfi_flash
2017-10-04 11:30:29 +01:00
a33f3178c2
adrv9371x/a10soc: For receive paths SYNC_TRANSFER must be enabled
2017-10-04 11:29:09 +01:00
899b8436ad
arradio: Fix the last incorrect merge
2017-10-03 09:15:45 +01:00
89bd8b44d4
Merge branch 'dev' into hdl_2017_r1
2017-09-26 07:42:19 +01:00
256dd87dd2
common/microzed: Enable PS CLK1 = 200MHz
2017-09-25 15:16:58 +03:00
07f3295638
common/a10soc: Update configuration for emif plddr4 IP
2017-09-25 08:57:26 +01:00
700ed156ab
[axi|avl]_dacfifo: Create a separate bypass module for altera/xilinx
2017-09-25 08:56:40 +01:00
3a47567f9c
common/a10gx: Chance SPI frequency from 128KHz to 10 MHz
2017-09-19 18:01:18 +03:00
cafa811c74
adrv9379: Change the DMA clock to 250
2017-09-11 16:52:44 +03:00
58572d746c
arradio/c5soc- rd10102013_979 fix
2017-09-05 12:52:41 -04:00
c3aa3e8a9c
adrv9371: a10soc: Whitespace cleanup
...
Remove some extra end-of-line whitespace.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-09-05 13:47:49 +02:00
6736aaeca1
arradio- add control/status ports
2017-09-01 14:39:18 -04:00
bb73e7a40f
arradio- add control/status ports
2017-09-01 14:39:18 -04:00
6ce4494002
adrv9379: Initial commit
2017-09-01 17:28:04 +03:00
Adrian Costina
AndreiGrozav
Lars-Peter Clausen
Istvan Csomortani
Michael Hennerich
Matt Fornero
STEVE KRAVATSKY
Rejeesh Kutty