Commit Graph

6 Commits (3f0a487b2e8f7425206bed310c45f2f313dee2b8)

Author SHA1 Message Date
Laszlo Nagy c3ae609bc8 data_offload: Refactor core
Deprecate unused parameters.

Change to MEM_SIZE_LOG2, to support only power of 2 storage sizes for
now. However in the future we might want to add support for non pow2
sizes so register map is not changed.

Change transfer length to -1 value to spare logic.

Change FIFO interface to AXIS to have backpressure, this allows the
implementation of data movement logic in the storage unit and let the
FSM handle high level control an synchronization and control the storage
unit through a control interface.

Refactor FSM to have preparation states where slow storages can be
configured and started ahead of the data handling.

Make bypasss FIFO optional since in some cases causes timing failures
due the missing output register of the memory. This can be targeted in
a later commit.

Hook up underflow/overflow to regmap useful in case of external memory
where rate drops due misconfiguration can be detected.

Cleanup for verilator.

Scripting:
Add HBM and DDR external memory support using util_hbm IP
Replace asym_block_ram with util_do_ram IP
2022-04-28 14:31:32 +03:00
Laszlo Nagy d94ec80e08 Update README.md
Correct the  ZCU102 PL DDR memory controller interface width and speed based on available options of the MIG
2021-10-05 11:59:51 +03:00
David Winter a89d0e6176 data_offload: Fix AXI register map
Signed-off-by: David Winter <david.winter@analog.com>
2021-08-06 11:55:24 +03:00
David Winter 537a284115 data_offload: Fix readme images
Signed-off-by: David Winter <david.winter@analog.com>
2021-08-06 11:55:24 +03:00
Istvan Csomortani 6516b09a31 data_offload: Update README and generic block design 2021-08-06 11:55:24 +03:00
Istvan Csomortani 86b611c1f7 data_offload: Initial commit 2021-08-06 11:55:24 +03:00