3f5d930cde
axi_adc_decimate/cic_decim: Fix clk_enable warning
...
- fix clk_enable zero replication warning
2017-05-16 19:35:24 +03:00
fd7db4fcf3
util_tdd_sync: add missing ports
2017-05-16 19:35:24 +03:00
cf3737122b
Remove duplicare wire declaration
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-Introduced by updating to verilog-2001
2017-05-16 19:35:24 +03:00
41e25e7c96
Add missing ad_serdes_out interface ports
2017-05-16 19:35:24 +03:00
0c5dabe358
axi_ad9963: Update constraints as adc_common and dac_common paths have been renamed
2017-05-15 18:59:09 +03:00
ce4f9bf906
up_dac_common: rename internal signals
2017-05-15 18:58:26 +03:00
ebeebdddf0
altera- infer latest versions
2017-05-12 13:40:14 -04:00
c728299e71
altera- default to latest version
2017-05-12 13:25:17 -04:00
ecfa15bfce
version check- change to critical warning
2017-05-12 09:51:48 -04:00
e4ae391237
axi adc cores: Add missing ports to up_adc_common instance
2017-05-12 13:39:05 +03:00
0e1e507541
axi dac cores: Add missing ports to up_dac_common instance
2017-05-12 13:37:34 +03:00
d93a6d062e
fmcadc5-sync: added a convenience timer
2017-05-11 12:39:39 -04:00
8e7b577c94
axi_ad5766: Add missing ports to up_dac_common instance
2017-05-11 17:25:31 +03:00
6e5d965211
axi_ad5766: sdo_mem size is 3
2017-05-11 17:25:31 +03:00
7968ca64a6
axi_ad5766: Delete redundant parameters
2017-05-11 17:25:31 +03:00
e327166cf2
axi_generic_adc: Update port names for up_adc_common instance
2017-05-11 11:00:24 +03:00
039ae9ae92
fmcadc5- syntax/port name fixes
2017-05-10 16:30:15 -04:00
fea6eb68be
up_adc_common- port name changes
2017-05-10 14:45:17 -04:00
c2dd991736
axi_fmcadc5- sign-extend and interleave (core is too late)
2017-05-10 14:33:56 -04:00
78435ebbb7
ad9625- add an option to control cs monitoring
2017-05-10 14:33:56 -04:00
d374f5b091
library/up_adc_common- add sref sync option
2017-05-10 14:33:56 -04:00
61bbfb2c82
library/axi_fmcadc5_sync- remove dependecy on adc-core (driver shows up late)
2017-05-10 14:33:56 -04:00
c44de7021a
axi_ad9739a: Fix DDS set frequency
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- DDS out frequency was 4 times greater than the desired frequency
2017-05-10 17:39:00 +03:00
5fe008d887
axi_ad9371: Update dac_clk_ratio to 2
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DAC sampling frequency is two times of the JESD204
core clock.
2017-05-10 11:12:45 +03:00
b6e9c92f46
axi_fmcadc5_sync- raw inputs & constraint fixes
2017-05-08 10:29:06 -04:00
391a14be7a
hdlmake.pl updates
2017-05-04 13:59:47 -04:00
1bd444b47f
axi_fmcadc5_sync- calcor added
2017-05-04 13:58:35 -04:00
f93a003ed1
axi_ad9434: Fix input data rate
2017-05-04 16:43:09 +03:00
6387b53266
ad77681evb: Initial commit
2017-05-04 12:19:11 +03:00
3ba57582bb
spi_engine_offload: Add a CDC module for trigger reception
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There are devices which have a asynchronous data ready signal. (asynchronous
with the spi clock) The CDC stages can be enabled by setting up
the ASYNC_TRIG parameter.
2017-05-04 12:14:06 +03:00
07956cfe66
spi_engine: Define parameter inside the module statement
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Part of the effort to update all verilog files to use the
ANSI-C style port list in module definitions. (verilog-2001)
2017-05-04 12:13:47 +03:00
d29f420ffa
axi_fmcadc5_sync: add a calibration signal generation
2017-04-28 11:13:24 -04:00
956753ca9c
hdlmake- updates
2017-04-27 15:11:01 -04:00
0cb2316cb9
fmcadc5-sync- add ldo psync
2017-04-27 13:26:17 -04:00
49ef9a589b
axi_ad5766: Fix parameter name for up_dac_common
2017-04-27 13:55:16 +03:00
4e15a21b79
spi_engine_interconnect: Delete dependency defined for S1_CTRL interface
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The S1_CTRL interface is not dependent of the number of SDI lines.
2017-04-27 11:28:25 +03:00
4ceed4d373
util_pulse_gen: Add Makefile
2017-04-27 11:28:25 +03:00
18a671cdb7
spi_engine: Expose DATA_WIDTH to software
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The value of DATA_WIDTH can be read back from register 0x44
The DATA_WIDTH will define the size of a word in a transaction.
2017-04-27 11:28:24 +03:00
801fb2281e
util_pulse_gen: The valid period is stored in pulse_period_d
2017-04-27 11:28:24 +03:00
fbccb377cc
adaq7980: Add an trigger generator for SPI offload
2017-04-27 11:28:23 +03:00
a4c422ac4c
spi_engine_execution: Define port dependencies for SDI ports
2017-04-27 11:28:21 +03:00
045cb96744
axi_spi_engine: Define ports dependencies for up_* interface
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The up_* interface ports are active just if the MM_IF_TYPE is UP_FIFO.
2017-04-27 11:27:35 +03:00
9cd218eb90
up_dac_common: Increase datawidth of dac_datarate
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In case of high precision devices with just a simple SPI interface
for control and data, the effective data rate can be significatly
lower than the SPI clock, and more importantly there isn't any relation
between the two clock domain.
The rate is defined by a SOT (start of transfer) generator, which
initiates a SPI transfer. Taking the fact that the generator runs
on system clock (100 MHz), and the device can require smaller rate (in kHz domain),
the 7 bit dac_datarate register is just too small.
Therefor increasing to 16 bit.
2017-04-27 11:24:08 +03:00
a2c20551a2
axi_ad5766: Add Makefiles for the core
2017-04-27 11:22:31 +03:00
eba22892b8
axi_ad5766: Preserve consistent coding style
2017-04-27 11:21:15 +03:00
d061104a3c
util_pulse_gen: Add configuration interface for 'pulse period'.
2017-04-27 11:21:12 +03:00
825d46259b
interface: Update spi_engine_offload_ctrl definition
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Because of the new AD5766 offload module, SDO lines are
defined as 'optional'.
2017-04-27 11:19:22 +03:00
5c5baf3abf
spi_engine: Fix CMD_FIFO_VALID generation
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Because of the memory map interface mux, up_waddr_s should be used,
when cmd_fifo_in_valid is generated.
2017-04-27 11:19:20 +03:00
29f0ce36bb
axi_ad5766: Initial commit
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This core can be used in conjunction with the SPI_ENGINE, will work
as an offload module, forwarding a data stream to the SPI excecution,
received from a DMA.
2017-04-27 11:16:23 +03:00
fb6e0d3efb
spi_engine: Add dependency for unused interfaces
2017-04-27 11:16:19 +03:00
AndreiGrozav
Adrian Costina
Rejeesh Kutty
Istvan Csomortani