Adrian Costina
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d43ba5d26e
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axi_ad9963: Integrated ADC/DAC clock enables
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2017-04-18 12:17:40 +02:00 |
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Adrian Costina
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3c13aa49eb
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axi_ad9963: Changed TX path from serdes to ddr.
- remove delay control related logic
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2017-04-18 12:17:39 +02:00 |
Lars-Peter Clausen
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72cdd846b0
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axi_ad9963: Allow to disable the IDELAYs on the ADC data path
Not all designs need the IDELAYs. Disabling them can reduce power consumption of the system.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
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2017-04-18 12:17:39 +02:00 |
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Adrian Costina
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094872619d
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axi_ad9963: Separated adc/dac clock and reset
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2017-04-18 12:17:39 +02:00 |
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Adrian Costina
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9f8fd5c922
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axi_ad9963: updated tx path
- removed pll for power saving, added serdes circuitry instead
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2017-04-18 12:17:39 +02:00 |
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Adrian Costina
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fb945ac51c
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axi_ad9963: Initial commit
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2017-01-31 16:18:58 +02:00 |