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4 Commits (40c9fc92c1887ac633f5c13ae64699baa7b62b39)

Author SHA1 Message Date
Adrian Costina d18f6aa816 adrv9371x: A10GX, added adcfifo 
- connected dac dma to 133 MHz clock
- set explicit clock rate to xcvr reference clock bridge
 2016-08-26 14:46:48 +03:00
Adrian Costina 215edb11c6 adrv9371: A10GX, updated design 
- disable reconfiguration for RX transceivers and enabled the reconfiguration for TX transceiver. They cannot be enabled at the same time at this point
- update FIFO SIZE to 16 for all DMAs
- updated memory connections to 256 bit and moved clock connection to 133 MHz, for all DMAs.
 2016-08-23 18:25:48 +03:00
Adrian Costina 41203d07e9 adrv9371x: A10GX, update SPI connection 2016-08-18 17:42:27 +03:00
Adrian Costina 5c27ccd1fa adrv9371x: Added common qsys tcl 2016-08-16 15:34:10 +03:00