4b08df9ed6
ad9361/tdd: Fix generation of tx_valid_* signals
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In FDD mode the tx_valid_* signals are generated inside the axi_ad9361_tx module, in function of
the selected dac data rate. In TDD mode, these signals are gated by the tdd_enable and tdd_tx_dp_en signals.
In other words, the tx_valid_* signals will be valid just when tdd_enable and tdd_tx_dp_en is active.
2015-06-08 16:23:32 +03:00
2e877389b2
ad9361_tdd: Some naming and hierarchical changes
2015-06-04 18:09:49 +03:00
3b1ea7e528
axi_ad9361/tdd: Cherry picked commit 598ece4 from hdl_2015_r1 branch
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598ece4c8d
2015-06-04 18:09:47 +03:00
6548bcd71f
axi_ip- constraints: add rst path
2015-06-04 10:53:13 -04:00
e7470036bf
library- drp moved to up clock
2015-06-01 13:39:26 -04:00
aa24c442f5
a10gx- no-ddr
2015-06-01 11:00:01 -04:00
92fc0e050d
altera- common sdc
2015-06-01 10:59:57 -04:00
83df53d9bf
adc_common: Updated version because the delay registers have been changed
2015-05-25 17:18:14 +03:00
1ef83bd88b
axi_ad9671: Updated port names. Fixed synchronization of the rx_sof with the ad_jesd_align module, so that data valid is assigned correctly
2015-05-23 00:16:27 +03:00
660c84e01c
axi_ad9434 : Update the IO delay interface
2015-05-22 19:47:09 +03:00
0c6ef203c0
iobuf: do is a system-verilog keyword
2015-05-21 14:06:13 -04:00
9762c65868
library- jesd-align port name change
2015-05-20 14:25:21 -04:00
6e047f78c6
delay-cntrl: up-clk, direct access + tx
2015-05-18 14:28:20 -04:00
a07d11c3e9
axi_ad9361_tdd: Define control bits for continuous receive/transmit
2015-05-14 17:21:32 +03:00
7c9bc40c75
axi_ad9361&TDD: Update TDD
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+ Delete unnecessary registers
+ Add the module ad_addsub.v to resolve additions and subtractions inside TDD control
+ Redefine the burst logic
+ Redesign the control signal generations
+ Note: This patch fix the TDD related timing violations
2015-05-13 14:03:01 +03:00
2e7135c3c2
axi_ad9361_tdd: Initial commit.
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Add the TDD register map and TDD control module. Add TDD integration changes to axi_ad9361 IP core.
2015-05-11 12:20:44 +03:00
d623f77453
axi_jesd_gt: Added rx_jesd_rst and tx_jesd_rst.
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Resets for both up clock domain and rx clock domain are needed in some projects
2015-04-30 12:07:36 +03:00
a7a2d194e9
axi_jesd_gt: Switched rx_rst and rx_rst_done to up clock domain, to be compatible with xilinx JESD core
2015-04-28 15:04:18 +03:00
7c97e192f2
dma_fifo: Simplify FIFO WE condition
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The only time we must not write to the FIFO is when it is full as this will
overwrite the first sample. Under all other conditions it is ok to write
data. If that data is invalid it will be overwritten when valid arrives.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-16 17:48:22 +02:00
b14721b8ae
library: Use common prefix for CDC signal names
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Use a common naming scheme for CDC signals to make it easier to create
constraints for them.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-15 17:20:22 +02:00
e116822059
imageon_zc706: Updates and fixes
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+ sync the sof to the dma_de signal
+ hdmi_rx_dma is connected to the HP1
+ fix syncronization signal in the CSC module
+ hdmi_rx_clk is asynchronous
2015-03-27 18:57:32 +02:00
552d9b41f7
imageon: updates
2015-03-24 15:08:48 -04:00
b29e97f985
hdmi_rx: imageon updates
2015-03-24 15:08:48 -04:00
80c2a5a45d
axi_hdmi_rx: General clean up
2015-03-23 12:39:26 +02:00
8dfcbdfd48
gt_channel/gt_common: simulation parameter warning fix
2015-03-06 12:36:07 -05:00
57e1f0e334
gt_channel/gt_common: simulation parameter warning fix
2015-03-06 12:36:03 -05:00
2d01955042
up_gt: change version dfe/lpm support
2015-03-05 09:47:16 -05:00
1613f7fb41
cftl_cip: Add util_pmod_fmeter IP to library
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Frequency meter IP for CN0332.
2015-02-23 17:20:12 +02:00
2442b6e929
gt- report device type
2015-02-17 11:43:50 -05:00
de043ce130
gt_channel: lpm/dfe programmable
2015-02-13 11:33:04 -05:00
870ebdb562
up_gt: support lpm mode
2015-02-12 16:21:11 -05:00
1e7c9a3924
gt_es: support lpm mode - 2/2
2015-02-12 16:20:43 -05:00
0a8e6f62ef
gt_es: support lpm mode - 1/2
2015-02-12 15:15:18 -05:00
9e2e2ef44e
xfer-logic: stretch toggles to allow capture
2015-02-06 22:15:16 -05:00
e9231c8f36
xfer-logic: stretch toggles to allow capture
2015-02-06 22:15:14 -05:00
9f485f2f4e
common: Add register map module for HDMI receiver.
2015-01-08 12:24:47 +02:00
161e6cc70d
common: Add color space sampling and color space conversion modules
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This two module are used by the HDMI receiver.
2015-01-08 12:24:46 +02:00
3a4d765a2b
up_clkgen: reading typo
2015-01-07 14:02:39 -05:00
1d6ea64d04
up_gt: move status to up clock
2014-12-16 08:48:13 -05:00
04c10abc2f
gth/gtx: share same cpll/qpll cpu settings
2014-12-11 11:18:48 -05:00
8cc9adfc49
up_axi: Fix up_raddr/up_waddr port width
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Make sure that the port declaration width matches with the reg declaration
later on.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-12-01 13:22:28 +01:00
a4724f8396
es: added kcu105 gth
2014-11-17 09:55:12 -05:00
b1c91fac92
es: added kcu105 gth
2014-11-17 09:55:10 -05:00
c6df568a00
Revert "ad_interrupts: Initial check in."
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This reverts commit b254380338
2014-11-06 12:16:52 +02:00
74ec396b27
ad_rst: ultrascale -dual stage
2014-11-05 16:47:41 -05:00
17cb1d9585
common/mem: asymmetric version
2014-10-30 11:12:09 -04:00
b254380338
ad_interrupts: Initial check in.
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Initial check in of the interrupt concatenation block.
2014-10-27 19:34:34 +02:00
7e52cf9568
up_axi: timeout generating multiple/repeated acks
2014-10-23 13:51:33 -04:00
1d26639d73
common: Added synchronization mechanism to the up_adc_common module
2014-10-22 10:05:55 +03:00
2817ccdb22
up_axi: altera can not handle same clock assertion of arready and rvalid
2014-10-09 15:25:05 -04:00
Istvan Csomortani
Rejeesh Kutty
Adrian Costina
Lars-Peter Clausen