73468d662b
axi_tdd: Add false paths to tdd sync input
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This allows the external synchronization input to be driven from
asynchronous sources like a 1 PPS signal or just signals from different
clock domains in general.
Signed-off-by: David Winter <david.winter@analog.com>
2022-04-20 10:54:53 +03:00
63089a7c5d
library/axi_ad9361/intel: Update I/O format
2022-04-08 11:00:04 +03:00
7a5ecb592e
library/data_offload: Remove empty module data_offload_control
2022-04-07 17:17:47 +03:00
18b5fabde0
library: Remove unused IPs
2022-04-06 14:57:37 +03:00
96adaf4fc7
cn0506_rgmii:a10soc: Remove project as the rgmii adapter is not compatible with a10soc
2022-04-05 14:49:47 +03:00
60be01f2eb
axi_clock_monitor: Fix various issues
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- Replace .xdc file
- Remove parameter dependency for wire signals
- Fix typo
- Remove unnecessary comments
- Fix signal width
2022-04-05 12:23:33 +03:00
fe713a5e98
library/axi_dmac: Rename 2d_transfer to dmac_2d_transfer
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Update the file according to HDL guideline.
Replace all occurrences of 2d_transfer with dmac_2d_transfer.
Update axi_dmac/Makefile.
2022-04-01 16:02:46 +03:00
d9ec44657f
libraries: Correct module name according to the filename
2022-04-01 16:02:46 +03:00
d40db9e204
adrv9009zu11eg: Added additional GPIOs and CS to the GPIO expander
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This should integrate seamlessly with SYNCHRONA14
2022-04-01 10:24:04 +03:00
6c0a07c24b
cn0506_mii/rgmii on a10soc: update to Quartus 21.2
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Remove contraints related to quartus version so that
cn0506_mii and cn0506_rgmii on arria10 to be built
with default quartus version.
Signed-off-by: stefan.raus <stefan.raus@analog.com>
2022-03-31 09:55:56 +03:00
6ea2a40a36
ad4630: Fix Readme
2022-03-30 08:34:18 +00:00
0d44bfb4dd
axi_hdmi_tx update for: ZedBoard, ZC706, ZC702, de10nano, ADRV9361-Z7035 ( #897 )
2022-03-29 16:51:21 +03:00
de70157e3a
xilinx/common:ad_data_out.v: Fix typo
2022-03-29 16:50:20 +03:00
204dff3b73
library: Adding axi_clock_monitor ip core
2022-03-29 10:02:42 +03:00
459704d183
Add small check to make sure readme.md files are in projects
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Signed-off-by: Robin Getz <robin.getz@analog.com>
2022-03-28 22:01:37 +03:00
64452a6c16
ad9083: Add reference design for ad9083_a10soc
2022-03-28 16:04:38 +03:00
31c21cad7f
xilinx/common: Add CLKEDGE parameter to ad_data_* module
2022-03-25 15:10:12 +02:00
e4832cd027
ad9208_dual_ebz: Update Board Product Page link
2022-03-25 10:42:40 +02:00
c1721e18dd
account for ADI_VIVADO_IP_LIBRARY global variable when adding subcores
2022-03-24 16:29:49 +02:00
0d9e9e42c0
sidekiqz2: Updated Readme to link the ADALM-Pluto documentation
2022-03-24 16:29:11 +02:00
aa1192a9bc
ad_quadmxfe1_ebz_bd: Connecting all the unused lanes in util_xcvr
2022-03-23 08:13:09 +02:00
101874de86
projects/scripts/adi_board.tcl: Fix padding error caused by lane_map in ad_xcvrcon procedure
2022-03-23 08:12:49 +02:00
6a252ec067
util_mii_to_rmii: Fix 100 Mbps configuration functionality
2022-03-22 14:30:24 +02:00
4499ddaae7
pluto_ng: Add Readme.md file
2022-03-22 11:43:44 +02:00
e22a597752
adrv2crr_fmcxmwbr1: Initial commit
2022-03-18 10:19:40 +02:00
084d44c978
add ability to customize Xilinx IP library version to value other than "user" from a global variable.
2022-03-17 09:43:39 +02:00
0f8cc9e66b
ad9083: Using variables instead of hard coded nets
2022-03-15 10:53:31 +02:00
8df1d8eade
ad9081_fmca_ebz: Update parameter description
2022-03-11 13:16:22 +02:00
5ced589258
ad9082_fmca_ebz: Update parameter description
2022-03-11 13:16:22 +02:00
081de06ec9
ad_quadmxfe1_ebz: Update parameter description
2022-03-11 13:16:22 +02:00
e66c5282bc
axi_adrv9001: Expose IODELAY_CTRL parameter to top level
2022-03-02 11:06:12 +02:00
a21cd9932d
adrv9001_zed: Fix irq overlap
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axi_adrv9001_tx1_dma/irq is no longer dissconnecting axi_iic_fmc/irq
2022-03-01 16:42:52 +02:00
d4fb7062d9
vcu128/vcu128_system_constr: Enable internal diff term for Ethernet clock
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There are no external termination resistors on the VCU118 and VCU128 for
the SGMII clock lines.
The board files of the VCU118 enables them, but this was not reflected in the
constraint files.
For VCU128 the clocking is similar, even if diff terms are not set in the
board files we should have a consistent approach with the VCU118.
2022-02-16 14:09:20 +02:00
c871a3a9ee
vcu118/vcu118_system_constr: Enable internal diff term for Ethernet clock
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There are no external termination resistors on the VCU118 for the SGMII
clock lines. The board files enables them, but this was not reflected in the
constraint files.
2022-02-16 14:09:20 +02:00
4c7be950d1
ad_ip_jesd204_tpl_adc: Fix latency of valid signal
2022-02-16 10:27:50 +02:00
5edf6c19de
adrv9009/zcu102: Hook up ref clock from IBUFDS_GT
2022-02-15 11:09:37 +02:00
4bd55dc5c2
adrv9009/zc706: Hook up ref clock from IBUFDS_GT
2022-02-15 11:09:37 +02:00
aac4746398
adrv9009/common/adrv9009_bd: Take ref clock from the IBUFDS_GT
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In some cases (GTX2) the transceiver may gate the out_clk when it is in
reset or misconfigured. This will stop the clock generators from getting
a clock prior removing the reset of the XCVR. The XCVR has a requirement
of running user clock while removing the reset. The correct sequence must be :
Enable device clocks (user clock)
Remove the reset from the XCVR
2022-02-15 11:09:37 +02:00
3c6c45962a
adrv9371x/kcu105: Hook up un-gated ref clock to fabric
2022-02-15 11:09:37 +02:00
572005abe4
adrv9371x/zcu102: Hook up un-gated ref clock to fabric
2022-02-15 11:09:37 +02:00
501903bc81
adrv9371x/zc706: Hook up un-gated ref clock to fabric
2022-02-15 11:09:37 +02:00
39e073e6bf
adrv9371x: Use the output of IBUFDS_GTE2 as reference for the clock gens
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In some cases (GTX2) the transceiver may gate the out_clk when it is in
reset. This will stop the clock generators from getting a clock prior
removing the reset of the XCVR. The XCVR has a requirement of running
user clock while removing the reset. The correct sequence must be :
Enable device clocks (user clock)
Remove the reset from the XCVR
2022-02-15 11:09:37 +02:00
86d754ae85
projects/scripts: Add gtwizard scripts
2022-02-14 10:32:58 +02:00
62dc310794
Revert "intel: Update projects to use ad_iobuf instead of ALT_IOBUF"
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This reverts commit a3a610728c
2022-02-09 17:39:29 +02:00
4790d334ad
dac_fmc_ebz: NUM_LINKS added to system_top.v
2022-02-09 12:23:12 +02:00
7702079af5
ad_quadmxfe1_ebz: Fix external sync for ADC path
2022-02-08 16:56:01 +02:00
3ff2887485
dac_fmc_ebz_vcu118: Initial commit
2022-02-08 14:34:47 +02:00
694ebbfbfc
dac_fmc_ebz_bd.tcl: Updated bd for multiple tx_ref_clk
2022-02-08 14:34:17 +02:00
45dae0f3d3
ad9081_fmca_ebz/common: Connect sync at TPL level
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Reset CPACK from ADC TPL so during armed capture clear the cpack to avoid
capturing old samples.
Reset UNPACK with TPL to clear upack during armed transfers to avoid
sending old data.
2022-02-07 19:14:01 +02:00
8ec657315c
adrv9009zu11eg: Drive cpack/upack reset from TPL
2022-02-07 19:14:01 +02:00
David Winter
Iulia Moldovan
Adrian Costina
AndrDragomir
stefan.raus
sergiu arpadi
PopPaul2021
Robin Getz
LIacob106
Nick Pillitteri
Filip Gherman
alin724
AndreiGrozav
Stanca Pop
Ionut Podgoreanu
Laszlo Nagy