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Author SHA1 Message Date
AndreiGrozav 7dcaaea04e library: Update scripts/adi_ad_ip.tcl and IPs 
Fix library makefiles dep list using generic vendor info reg

Combine adi_int_bd_tcl with adi_auto_fill_bd_tcl procedure.
This change will simplify the process of generating makefiles for each library.
Removing the bd.tcl script from the adi_ip_files list will remove it from the
make dependency list.
 2019-04-09 16:07:14 +03:00
AndreiGrozav 4ae5a6d3d8 library/IPs: Auto-generate bd.tcl Update 
Remove all bd.tcl and respecting the previous commit, update *_ip.tcl to
auto-generate bd.tcl for:

  - axi_ad5766/axi_ad5766_ip.tcl
  - axi_ad6676/axi_ad6676_ip.tcl
  - axi_ad9122/axi_ad9122_ip.tcl
  - axi_ad9144/axi_ad9144_ip.tcl
  - axi_ad9152/axi_ad9152_ip.tcl
  - axi_ad9162/axi_ad9162_ip.tcl
  - axi_ad9250/axi_ad9250_ip.tcl
  - axi_ad9265/axi_ad9265_ip.tcl
  - axi_ad9361/axi_ad9361_ip.tcl
  - axi_ad9371/axi_ad9371_ip.tcl
  - axi_ad9434/axi_ad9434_ip.tcl
  - axi_ad9467/axi_ad9467_ip.tcl
  - axi_ad9625/axi_ad9625_ip.tcl
  - axi_ad9671/axi_ad9671_ip.tcl
  - axi_ad9680/axi_ad9680_ip.tcl
  - axi_ad9684/axi_ad9684_ip.tcl
  - axi_ad9739a/axi_ad9739a_ip.tcl
  - axi_ad9963/axi_ad9963_ip.tcl
  - axi_adrv9009/axi_adrv9009_ip.tcl
  - axi_fmcadc5_sync/axi_fmcadc5_sync_ip.tcl
  - axi_hdmi_tx/axi_hdmi_tx_ip.tcl
  - xilinx/axi_adxcvr/Makefile
  - xilinx/axi_adxcvr/axi_adxcvr_ip.tcl
  - xilinx/util_adxcvr/Makefile
  - xilinx/util_adxcvr/util_adxcvr_ip.tcl
 2019-03-30 11:26:11 +02:00
AndreiGrozav 66823682b6 Add FPGA info parameters flow 
Common basic steps:
- Include/create infrastructure:

   * Intel:
       - require quartus::device package
       - set_module_property VALIDATION_CALLBACK info_param_validate

   * Xilinx
       - add bd.tcl, containing init{} procedure. The init procedure will be
         called when the IP will be instantiated into the block design.
       - add to the xilinx_blockdiagram file group the bd.tcl and common_bd.tcl
       - create GUI files

- add parameters in *_ip.tcl and *_hw.tcl (adi_add_auto_fpga_spec_params)
- add/propagate the info parameters through the IP verilog files

axi_clkgen
util_adxcvr
ad_ip_jesd204_tpl_adc
ad_ip_jesd204_tpl_dac
axi_ad5766
axi_ad6676
axi_ad9122
axi_ad9144
axi_ad9152
axi_ad9162
axi_ad9250
axi_ad9265
axi_ad9680
axi_ad9361
axi_ad9371
axi_adrv9009
axi_ad9739a
axi_ad9434
axi_ad9467
axi_ad9684
axi_ad9963
axi_ad9625
axi_ad9671
axi_hdmi_tx
axi_fmcadc5_sync
 2019-03-30 11:26:11 +02:00
Lars-Peter Clausen d26f929ecc axi_ad9152: Use the generic JESD204 DAC transmitter core 
Replace the axi_ad9152 implementation with the new generic JESD204
interface DAC core. The replacement is functionally equivalent.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2018-05-02 17:21:20 +02:00
Lars-Peter Clausen bd251a5fd5 Remove unused DMA overflow signal from DAC DMA interfaces 
The DAC DMA will never overflow and unsurprisingly the dac_dovf signal is
never used anywhere. It is very unlikely it will ever be used, so remove
it.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2018-05-02 17:21:20 +02:00
Adrian Costina 74b922f9f8 axi_*: Infer clock and reset signals of an IP 
A clock sink must be connected to clock source, and a reset sink to
reset source, otherwise the tool will throw a synthesis warning.
By properly inferring all the reset and clock signals of an IP, we can
get rid of unwanted warning messages.

The following IPs tcl script was updated:
  - axi_ad9434
  - axi_hdmi_tx
  - util_cpack
  - util_adxcvr
  - axi_ad6676
  - axi_ad9625
  - axi_ad9379
  - axi_ad9265
  - util_tdd_sync
  - util_rfifo
  - util_wfifo
  - axi_ad9361
  - axi_ad9467
  - util_upack
  - axi_dacfifo
  - axi_ad9152
  - axi_ad9680
  - util_clkdiv
  - axi_ad9122
  - axi_ad9684
  - axi_mc_speed
  - axi_mc_current_monitor
  - axi_mc_controller
  - util_gmii_to_rgmii
  - util_adxcvr
  - axi_ad9379
  - axi_hdmi
  - library
  - axi_fmcadc5_sync
  - util_adcfifo
  - util_mfifo
  - axi_jesd204_rx
  - axi_jesd204_tx
  - axi_ad9361
  - axi_adxcvr_ip
 2018-04-11 15:09:54 +03:00
Istvan Csomortani c1bdfca4c3 library: Delete all adi_ip_constraint process call 2017-04-06 12:36:47 +03:00
Istvan Csomortani 873fbfd6d7 library: Update scripts with new constraints 
Update all IPs tcl scripts with the new constraints files.
Refer to commit 335fef0.
 2017-03-30 16:16:02 +03:00
Rejeesh Kutty 862bd7ef2c daq3/zc706- xcvr changes 2016-11-23 15:02:20 -05:00
Istvan Csomortani df36902713 lib_refactoring: Fix path of the IO macros 2016-08-08 15:07:19 +03:00
Rejeesh Kutty 54fcf06eed ad9152- ip updates 2015-09-30 11:34:09 -04:00
Istvan Csomortani 7b858bc5ad Revert commit 6b99ce 
Revert 6b99ce2482
 2015-08-26 13:48:28 +03:00
Adrian Costina 6b99ce2482 library: Added common constraints for all cores. Commented code that needs to be updated to 2015.2 2015-08-20 18:17:38 +03:00
Lars-Peter Clausen 6862655b0d Add .gitattributes file 
Add .gitattributes file which sets up the eol encoding handling. This will
make sure that we get a uniform eol encoding across different operating
systems.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2015-06-26 11:07:10 +02:00
Adrian Costina 8a1f4bf5f6 ad6676,ad9144,ad9152,ad9234,ad9250,ad9434,ad9467,ad9625,ad652,ad9671,ad9680,ad9739a:Set default driver value for overflow, underflow, gpio_in and dac_sync ports 2015-06-09 14:21:12 +03:00
Rejeesh Kutty 91b0f70972 library: remove drp cntrl 2015-06-02 09:58:57 -04:00
Lars-Peter Clausen 3a02998e9a axi_ad9152/axi_ad9152_ip.tcl: Fix typo 
axi_ad9152_constr.v -> axi_ad9152_constr.xdc

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2015-04-24 09:41:43 +02:00
Adrian Costina 09f05cf8e9 axi_ad9152: Added CDC and reset constraints 2015-04-23 10:21:52 +03:00
Rejeesh Kutty c375b5b26e daq3: vivado build 2014-10-06 10:34:02 -04:00
Rejeesh Kutty d47776a4a0 ad9152: 9144 copy 2014-10-06 10:34:01 -04:00