9b6dd27c23
ad9361- delay initialization
2017-03-15 12:06:59 -04:00
09bcecb6ed
m2k: Simplify DMA connection to HP1
2017-03-15 15:11:30 +02:00
2a9b3cea09
m2k: Changed the way DMAs connect to the PS7 DDR, to optimize resources use
2017-03-14 13:57:50 +02:00
f7c2bd943b
m2k: Enable AD9963 adc data path processing.
...
- part of the path is the sign extension module. Without it, the triggering doesn't work correctly
2017-03-13 23:18:29 +02:00
c3c8c366d3
axi_ad9361- add receive init delay
2017-03-13 16:28:53 -04:00
dac75f79ab
fmcomms5/usrpe31x- add iodelay report
2017-03-10 13:38:27 -05:00
1b3f752c3d
pzsdr1/pzsdr2/pluto- add iodelay report
2017-03-10 12:55:22 -05:00
0ae79ca7ac
move/rename - delay script belongs to ad9361
2017-03-10 12:44:32 -05:00
e736504e0f
fmcjesdadc1, usdrx1: Using the same clock in rx_data path
2017-03-10 14:26:51 +02:00
d08d1d5a1b
adrv9371x ,daq3, fmcomms7, fmcomms11: add dac_fifo missing reset connection
2017-03-10 14:20:42 +02:00
452e5e5ce0
fmcomms2- add delay reporting for iodelay
2017-03-09 15:29:15 -05:00
8bdfbe2b0a
fmcomms2- report delays
2017-03-09 15:21:42 -05:00
7e5d8664ad
fmcjesdadc1_a5gt: rx_data pins are all associated to the same clock
2017-03-09 08:57:03 +02:00
0e002f2f31
daq3_a10gx: Set XCVR Tx/RX clk/data voltage levels at 1V
2017-03-09 08:50:55 +02:00
191669ad28
daq2_common: Fix the dac_rst for DAC FIFO
2017-03-07 16:13:46 +02:00
fc8af6903f
pzsdr2/ccfmc- add rf input protection
2017-03-06 16:19:55 -05:00
3fa9a30f0e
a10soc/plddr4- lower mem clk to meet timing
2017-03-06 14:12:25 -05:00
38a27d02f6
a10soc/plddr4- differential refclk
2017-03-06 14:11:36 -05:00
936c441763
adrv9371x- dacfifo bypass-gpio control
2017-03-06 10:35:09 -05:00
762276a880
adrv9371x- dacfifo changes
2017-03-06 10:33:52 -05:00
4a6fe54fcf
daq2_common: Update common scripts
...
Add new port connection for util_dacfifo
2017-03-03 18:49:10 +02:00
ec89b1a45f
altera/adrv9371x- add dacfifo
2017-03-01 15:52:07 -05:00
bc6a09c828
adrv9371x/a10soc- dacfifo added
2017-03-01 15:35:04 -05:00
5b5c0dde99
ad6676evb: Set default xcvr parameters to common design
2017-03-01 11:32:17 +02:00
b78e9d8c27
daq2_a10gx: Set XCVR Tx/RX clk/data voltage levels at 1V
2017-03-01 11:32:17 +02:00
0cc5130c9a
adrv9371x: Set XCVR Tx/RX clk/data voltage levels at 1V
2017-03-01 11:32:17 +02:00
c1be17a3af
Altera a10 devices: disable warnings regarding unused channels
2017-03-01 11:32:17 +02:00
dc168f41fe
adrv9371_a10soc: Fixed port assignments
2017-03-01 11:32:17 +02:00
aad41039bd
a10soc- plddr4 settings
2017-02-28 13:36:28 -05:00
59dda01419
m2k: Disabled DDS cores for the generic project
2017-02-28 10:10:28 +02:00
fb4a583613
projects/system_bd- adc/dac fifo board designs
2017-02-27 16:06:39 -05:00
6b1a8852a9
dacfifo- bypass port name change
2017-02-27 16:06:39 -05:00
19c7b5d340
fmcadc5- move adc fifo settings to system-board
2017-02-27 16:06:39 -05:00
c1aac4a9fb
common: adc/dac fifo board designs
2017-02-27 16:06:39 -05:00
545e458997
m2k: Standalone, ignored critical warning for contraints that should only be applied at the implementation stage
2017-02-27 14:17:29 +02:00
eda585f0e4
m2k: Connected data[0] and trigger[0] pins to the logic analyzer clock generator input 2
2017-02-27 14:16:32 +02:00
908da60ab6
m2k: zed, changed constraints so they are the same with the ZED default configuration
...
- the voltage can be physically changed between 1.8V, 2.5V and 3.3V
2017-02-27 14:13:34 +02:00
0059c907ea
adrv9371: Drive the TX DMA interface with sys_dma_clk
2017-02-24 15:50:12 +02:00
ac2e5a9dac
constraints: Update constraints
...
Xilinx recommends that all synchronizer flip-flops have
their ASYNC_REG property set to true in order to preserve the
synchronizer cells through any logic optimization during synthesis
and implementation.
2017-02-24 13:43:32 +02:00
1fce57f6c3
axi_dacfifo: Redesign the bypass functionality
2017-02-23 17:32:31 +02:00
c598e84258
remove processing order (no clock def dependency)
2017-02-22 16:02:08 -05:00
edd5e9570f
file renamed; sed output; fingers crossed
2017-02-22 15:56:37 -05:00
b00dc4b195
plddr3- change to board files
2017-02-22 15:22:50 -05:00
89b49d2f67
fifo- as board files
2017-02-22 15:18:50 -05:00
879ed64bb6
compression flag changes
2017-02-22 15:15:53 -05:00
8a5e2ff46e
sys_wfifo- removed
2017-02-22 15:13:18 -05:00
754ac6a403
w/r-fifo- removed
2017-02-22 15:10:06 -05:00
040b61de60
fmcadc5: Updated default parameters
2017-02-20 17:13:58 +02:00
a15e05c497
adcfifo- remove axi-byte-width parameter
2017-02-17 15:29:10 -05:00
cb3d1883bc
fmcjesdadc1/a5gt- hard placement of ddr hr/qr registers
2017-02-17 15:21:33 -05:00
e8bcbb74da
scripts: fixed tcl syntax for altera projects not meeting timing
2017-02-16 21:21:51 +02:00
95a4ea20c8
axi_dacfifo: Delete redundant parameter BYPASS_EN
2017-02-16 19:53:44 +02:00
8453d758c2
scripts: If an altera project doesn't meet timing, rename the sof
2017-02-16 19:20:49 +02:00
343d0472d4
fmcadc2: Move GT setting to common/system_bd.tcl
2017-02-16 14:56:25 +02:00
07184b31d2
fmcadc2: Define default clock selection for Xilinx GTs
2017-02-16 12:35:24 +02:00
86c279c238
pzsdr1: ccbox, moved I2S core to DMA0 and DMA1 to fix critical warnings
2017-02-14 14:51:49 +02:00
46290193f3
pzsdr2: ccusb, renamed clk_out to clkout_in
2017-02-14 11:58:11 +02:00
27119343f2
pzsdr2: ccusb, connect unused clock pins to GND
2017-02-14 11:56:54 +02:00
fa37f4dd0a
pzsdr2: Don't set a disabled parameter
2017-02-14 11:56:08 +02:00
6a9b7580de
pzsdr1: ccusb, renamed clk_out to clkout_in
2017-02-14 11:54:46 +02:00
acef0113d1
pzsdr1: ccusb, connect unused clock pins to GND
2017-02-14 11:50:37 +02:00
46883731eb
pzsdr1: Don't set a disabled parameter
2017-02-14 11:50:06 +02:00
a569b6bf0c
pluto: Interpolation, connect fifo_rd_valid to s_axis_data_tvalid
2017-02-13 18:08:52 +02:00
e215a091b2
m2k: standalone, added explicit fclk_clk0 and fclk_clk1 constraints
2017-02-13 12:02:59 +02:00
4e62fb0ef3
m2k: Add reset circuitry on the logic_analyzer clock domain
2017-02-13 12:02:11 +02:00
5fa6dba333
Make: Update Makefiles
2017-02-10 16:32:58 +02:00
f5f1f47691
ad9467_fmc: Delete asynchronous clock group definition
...
This is a very bad way to handle timing. All the false path
should be defined explicitly, rather than define asynchronous clock
domains.
2017-02-10 16:21:35 +02:00
c39ed08edd
zcu102/*- actual clock == desired clock
2017-02-06 12:53:47 -05:00
58872aa3ef
fmcomms2/zc706pr- prcfg is a single clock synchronous design
2017-02-06 10:59:18 -05:00
971bcbb0fc
fmcomms1: Remove project
2017-02-03 16:42:44 +02:00
096274a033
daq2/zcu102- fix refclock pin swap
2017-02-03 09:26:07 -05:00
7c363cd5a7
daq3/a10gx/system_constr.sdc- fix typo
2017-02-03 09:26:07 -05:00
35f660fe06
fmcjesdadc1/vc707- constraint clean-up
2017-02-02 15:05:49 -05:00
d46352928a
fmcomms5- fix ovf net connections
2017-02-02 14:24:06 -05:00
6aadb49e80
m2k: Remove use board flow from the standalone version
2017-02-02 12:58:58 +02:00
0d0c3e99fd
m2k: Added I2C pull-ul, removed SLEW constraints
2017-02-02 12:35:46 +02:00
85ff496c12
daq2/a10gx- gpio match with others
2017-02-01 20:54:56 -05:00
5155b3f46d
m2k: Fix gpio buswidth
2017-02-01 17:43:01 +02:00
cfff70d358
M2K: Update standalone project
...
- configured PS7 similar to pluto. Added specific constraints instead of default PS7
- moved ad9963_resetn and en_power_analog to gpio[0] and gpio[1]
2017-02-01 14:27:11 +02:00
6bdd853b88
m2k: Updated PS7 configuration
2017-01-31 23:08:53 +02:00
b14d740f87
M2K: initial commit
2017-01-31 16:43:40 +02:00
d5af828b9c
Merge branch 'dev' into hdl_2016_r2
2017-01-30 17:10:05 +02:00
97d72d2f65
a10gx- xilinx/altera sync-up
2017-01-30 10:01:28 -05:00
b14e7fe4ee
daq3/kcu105- 1.25GSPS
2017-01-30 10:01:28 -05:00
48ad24cdbe
enable partial reconfiguration mode
2017-01-27 09:26:53 -05:00
be1328c55b
kcu105- added missing ethernet configurations
2017-01-23 10:14:09 -05:00
661413627f
daq3- round about way to avoid ip getting locked
2017-01-20 15:55:33 -05:00
62792ddaed
adrv9371x: Change the axi_adxcvr cores addresses
...
Because the S_AXI interface of the axi_adxcvr core was infered
using the process adi_ip_properties, the interface address range
has changed from 4k to 64k. As a result, all the addresses of
the axi_adxcvr cores were changed and realigned.
2017-01-19 15:23:03 +02:00
ecd152c90d
pzsdr1: ccbrk_cmos, fix clkdiv parameters
2017-01-18 12:04:04 +02:00
165ba76d9d
pzsdr1: Added FIFOs for DAC and ADC paths so that they work at l_clk or l_clk/2
2017-01-18 12:01:24 +02:00
319a883c00
pzsdr2: Added FIFOs for DAC and ADC paths so that they work at l_clk/2 or l_clk/4
2017-01-18 12:00:10 +02:00
9344dd34dc
zcu102: Update project to include clkdiv
2017-01-16 14:47:31 +02:00
4dcad7e116
fmcomms2: zcu102, update clkdiv device parameter
2017-01-16 14:38:37 +02:00
b622b6592e
FMCOMMS5/ZCU102 : Merge from njpillitteri/hdl:dev
...
Pull request Dev #26
2017-01-13 14:47:16 +02:00
d2e7b6b635
fmcomms5: Added FIFOs for DAC and ADC paths so that they work at l_clk/2 or l_clk/4
2017-01-13 14:18:59 +02:00
a36057679a
fmcomms2: Update Makefiles
2017-01-13 14:16:21 +02:00
15c5bc7012
fmcomms2: zcu102, changed clkdiv C_SIM_DEVICE parameter to ultrascale
2017-01-13 13:57:32 +02:00
b84325d43f
fmcomms2: take into consideration both adc_r1 and dac_r1 for clock division selection
2017-01-13 13:56:04 +02:00
f003b5b35a
fmcjesdadc1: Reduce SYSREF period
2017-01-12 16:10:45 +02:00
e77428c50e
fmcomms2: Added FIFOs for DAC and ADC paths so that the path works at l_clk / 2 or l_clk /4
...
- removed ILA
2017-01-11 18:12:35 +02:00
37d54bb984
fmcjesdadc1/a5gt- max delay fit only
2017-01-04 16:04:19 -05:00
8b74e911b8
fmcjesdadc1/a5gt- qr to ddio max delay
2017-01-04 14:10:44 -05:00
e4e5b30ade
fmcadc5: Integrate ad_sysref_gen into the project
2017-01-03 13:52:39 +02:00
14ded4f123
fmcjeadadc1/a5soc- ad_sysref_gen updates
2016-12-22 15:59:45 -05:00
b089173b4c
fmcjesdadc1/a5soc- cpu clock is 50m for a5gt also
2016-12-22 14:14:21 -05:00
aa6c94c993
usdrx1/a5gt: ddr3 use ip constraints
2016-12-22 14:14:21 -05:00
18660c7ab4
fmcjesdadc1/a5gt: ddr3 use ip constraints
2016-12-22 14:14:21 -05:00
2bea337aa2
fmcjesdadc1/a5gt- use 50m-mem-cpu-clk
2016-12-22 14:14:21 -05:00
5d683943ab
fmcjesdadc1/a5gt- remove ad-sysref-gen-pack
2016-12-22 14:14:21 -05:00
f1168f9e29
fmcjesdadc1/a5gt- use xilinx setup 2-dma
2016-12-22 14:14:21 -05:00
1ceec2e2a9
projects/a5gt- use 50m afi clock for cpu- xcvr reconfig timing
2016-12-22 14:14:21 -05:00
eba30b0cde
projects/altera- qii_auto_pack option
2016-12-22 14:14:21 -05:00
4a783d523d
projects/altera* - default & common qsys commands
2016-12-20 16:27:44 -05:00
3e57ff1fc5
z-mpsoc- map 0x4-0x8,0x7-0x9
2016-12-20 16:14:38 -05:00
1156aeac16
ad_sysref_gen: Update SYSREF related constraints
2016-12-19 18:07:05 +02:00
da7f4608a8
fmcjesdadc1/usdrx1: Clean up the mess
...
Delete accidentally commited generated files.
2016-12-19 15:35:20 +00:00
f47863bbcf
usdrx1: Integrate ad_syref_gen into the project
2016-12-19 14:36:01 +00:00
8d799d0316
fmcjesdadc1: Intergrate ad_sysref_gen into project
2016-12-19 13:37:29 +00:00
0c42e04bc3
fmcadc2: Integrate ad_sysref_gen into the project
2016-12-19 12:16:05 +00:00
67390c2a95
ad6676evb: Update projects with ad_sysref_gen
2016-12-19 10:52:25 +00:00
8879218502
a5gte: Fixed timing violations
2016-12-16 15:37:51 +02:00
c0b0f9b7e9
ad6676evb: Connect SYS_REF to GPIO
2016-12-14 17:55:50 +02:00
557efed5d9
ad6676evb: Update clock constraints
2016-12-14 17:55:49 +02:00
3a2c889115
ad6676evb: Update GT configuration
2016-12-14 17:55:49 +02:00
d962614000
usdrx1/zc706: Disabele axi_spi constraint file
...
The interface ports of the AXI SPI IP are not connected
directly to a IOBUF, this results in a CRITICAL WARNING
2016-12-13 19:23:51 +02:00
d5165ca81f
motcon_fmc: Tie unused pins to GND
2016-12-13 19:20:13 +02:00
1515b6f1af
fmcomms7/zc706: Disabele axi_spi constraint file
...
The interface ports of the AXI SPI IP are not connected
directly to a IOBUF, this results in a CRITICAL WARNING
2016-12-13 19:18:18 +02:00
8846141467
fmcomms1/kc705: Disabele axi_spi constraint file
...
The interface ports of the AXI SPI IP are not connected
directly to a IOBUF, this results in a CRITICAL WARNING
2016-12-13 19:16:31 +02:00
c455d2d64f
fmcadc2/vc707: Disabele axi_spi constraint file
...
The interface ports of the AXI SPI IP are not connected
directly to a IOBUF, this results in a CRITICAL WARNING
2016-12-13 19:15:44 +02:00
8ebc8fe4e2
updated makefiles
2016-12-09 23:06:41 +02:00
06aab8ebbd
pzsdr1: Set the device core to 1R1T mode
2016-12-09 16:35:46 +02:00
8e69c838e1
common/ac701: Connect axi_ddr_cntrl/device_temp_i to GND
2016-12-09 13:54:39 +02:00
23c91ca48a
pzsdr1/lvds: The interface runs at max 122.88 MHz
2016-12-09 11:45:11 +02:00
f799c40cf0
usdrx1/a5gt- xcvr interface changes
2016-12-08 16:05:23 -05:00
c114888956
usdrx1- updates
2016-12-08 16:05:23 -05:00
b0eff57b0f
fmcomms2/zc702: Fix critical warnings
2016-12-08 19:54:52 +02:00
3dceb53984
fmcadc2/vc707: Fix timing violations
2016-12-08 19:51:18 +02:00
252c67ceff
fmcomms6: Delete project
...
This project will not be supported in further releases.
2016-12-08 17:22:41 +02:00
fb287d0178
kcu105- updates to match xilinx trd
2016-12-08 09:32:33 -05:00
3bc9df4c51
fmcomms5: Fixed the wornings created by TDD missing connections to axi_ad9361 core
2016-12-07 21:43:19 +02:00
8eaae98728
fmcadc2: Updates
2016-12-07 21:43:19 +02:00
801da3cb25
daq3/kcu105- fix timing violations
2016-12-06 12:31:40 -05:00
2d7fb03b93
adrv9371x/a10gx- fix os xcvr parameters
2016-12-06 12:31:40 -05:00
ad96c5e881
daq3/zc706: Change the speed grade of the FPGA to 3
2016-12-06 15:24:23 +02:00
8f94103f8b
daq1/a10gx: Makefile fix
2016-12-06 15:24:23 +02:00
95ee7c093c
daq1/a10gx: Update system_bd port names
2016-12-06 15:24:23 +02:00
b7143a7a3b
daq1/a10gx: Update IO pin assignments
2016-12-06 15:24:22 +02:00
a415625069
daq1/a10gx: Add spi wrapper file to the project
2016-12-06 15:24:22 +02:00
e30a80fda0
daq1_spi: Delete device specific macro instantiation
2016-12-06 15:24:21 +02:00
7a8dc92b84
usb_fx3: Add interrupt monitor and increase ILA data depth
2016-12-06 11:55:28 +02:00
1e4bdea80c
usrpe31x: Fix Makefile
2016-12-06 11:07:42 +02:00
4b7bf422ee
pzsdr2/ccbox- remove imu intr on pl
2016-12-05 10:21:42 -05:00
351811e13f
pzsdrx/ccbox- imu intr on gpio
2016-12-05 10:18:40 -05:00
170c781d02
hdlmake.pl- updates
2016-12-01 13:52:11 -05:00
6e89ac3d65
pzsdr2: ccusb_lvds, add flag_a,flag_b signals
2016-11-30 17:39:02 +02:00
0faa1ebff2
pzsdr1: ccusb_lvds, add flag_a,flag_b signals
2016-11-30 17:38:04 +02:00
84a76b9dea
imageon: Invert HDMI TX clock
...
The ADV7511 samples the parallel data bus at the rising edge of sample
clock. Generate the clock so that the falling edge is aligned to updating
the bus data. This creates larger timing margins on each side of the
sampling edge and makes the design more robust.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2016-11-29 15:43:24 +01:00
24cc8d284b
imageon: Increase RX DMA FIFO size
...
Increase the RX DMA FIFO to be able to better compensate for momentarily
memory bus contention. This has shown to resolve occasional overflows that
would occur under high system memory load.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2016-11-29 14:12:39 +01:00
99dae73d96
imageon: Connect hdmi_rx_core output clock to DMA
...
Connect the HDMI RX core output clock to the DMA rather than connecting the
HDMI RX input clock directly. This will allow the HDMI RX core to modify
the clock and e.g. insert clock buffers or similar.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2016-11-29 14:12:39 +01:00
07217740b5
imageon: Increase HDMI RX clock constraint
...
The ADV7611 is rated for a maximum clock rate of 165MHz. Increase the clock rate constraint to match this.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2016-11-29 14:12:39 +01:00
284fbac571
usdrx1: Xcvr updates, so that the channel parameters are correctly configured from boot time
2016-11-28 14:16:07 +02:00
45fd4f806d
fmcjesdadc1: Fixed RX_PMA_CFG parameter
2016-11-25 16:33:58 +02:00
11b57290f1
fmcadc5- replaced with axi_adxcvr
2016-11-23 16:22:05 -05:00
22e230618c
scripts/adi_board.tcl- support multiple xcvrs
2016-11-23 16:22:05 -05:00
862bd7ef2c
daq3/zc706- xcvr changes
2016-11-23 15:02:20 -05:00
4e3e623530
pzsdr2/ccpci- updates
2016-11-23 14:02:59 -05:00
e5d3bae54d
projects/ad6676-adrv9371: xcvr updates
2016-11-23 11:06:22 -05:00
daa3df4b96
projects/- xcvr updates
2016-11-22 16:23:05 -05:00
8f562fd069
xcvr updates- board procedure
2016-11-22 14:43:36 -05:00
b1a9bd96f1
daq2: xcvr pll changes
2016-11-22 12:53:29 -05:00
750b23621b
board-tcl: xcvr qpll/cpll changes
2016-11-22 12:53:02 -05:00
4ed7469286
fmcadc4/zc706- updates
2016-11-22 10:32:05 -05:00
8c4279f618
pzsdr1: Added ccusb_lvds initial project
2016-11-22 16:58:34 +02:00
3d0049d274
pzsdr2: ccusb_lvdsr, updated project for the latest schematic
2016-11-22 16:55:52 +02:00
aff45eae5f
fmcadc2: xcvr updates
2016-11-21 18:45:38 +02:00
69ee410d3d
fmcomms2/zc706pr- bypass pr as default
2016-11-21 09:45:10 -05:00
4739d05269
zc706pr/common- removed
2016-11-18 14:52:39 -05:00
f43248c2bc
common/pzsdr*- removed
2016-11-18 11:32:43 -05:00
0d75bcb606
pzsdr2: ccbox: Use DMA interface 0+1 for audio
...
There is a bug in the ps7 component specification that causes critical
warnings to appear in the build log if DMA interface 0 is disabled, but any
other DMA interface is enabled.
Work around this issue by using DMA interface 0 and 1 instead of 1 and 2
for the I2S DMA.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2016-11-18 14:03:46 +01:00
b62f60b0da
pzsdr1/ccbox- updates
2016-11-17 16:14:28 -05:00
935f8a5c7b
pzsdr1/ccbox- constraints
2016-11-17 16:13:53 -05:00
4f65bcb3b2
pzsdr1/ccbrk_cmos- updates
2016-11-17 15:32:49 -05:00
e85dd2740a
pzsdr1/ccbrk_lvds- updates
2016-11-17 15:32:25 -05:00
a61da1d2ac
pzsdr1/common- updates
2016-11-17 15:31:25 -05:00
aa02ca875f
pzsdr1- common files
2016-11-17 13:40:25 -05:00
8c25402d53
pzsdr1- common files
2016-11-17 13:40:04 -05:00
4dae754287
pzsdr1- added readme
2016-11-17 11:29:01 -05:00
778638a7a1
pzsdr2- make updates
2016-11-17 10:26:45 -05:00
74bf4dfb80
pzsdr2- gpio- turn-around
2016-11-17 10:24:50 -05:00
d0166a4c7e
ccbox- updates
2016-11-17 10:24:11 -05:00
c2b7cbd61b
ccbox- constraints
2016-11-17 10:23:51 -05:00
5e6b931150
ccbox- added
2016-11-17 09:28:33 -05:00
fb5d36b250
pzsdr2- update ccfmc
2016-11-16 16:27:41 -05:00
95c44b687e
pzsdr2- fmc/pci constraints
2016-11-16 16:27:41 -05:00
11347c49be
fmcomms11- device set to -3
2016-11-16 13:43:07 -05:00
b85a282748
fmcomms11- lane swap
2016-11-16 10:26:47 -05:00
bdd14c3874
README: Delete second rule under headers
...
By default there is a rule under each header, no need for another one.
2016-11-16 11:04:43 +02:00
81e47edcd5
README: Set links for documentation
2016-11-16 10:57:39 +02:00
fabbe4981e
Update README.md
...
updated
2016-11-15 16:15:55 -05:00
538a1c977f
pzsdr2: make files
2016-11-15 16:00:55 -05:00
4905e80df8
Update README.md
...
updated
2016-11-15 14:16:46 -05:00
db243df97e
pzsdr2- updates
2016-11-15 14:16:06 -05:00
0897716167
fmcadc4: xcvr updates
2016-11-15 16:03:52 +02:00
cac4057449
daq2/common: Altera updates
2016-11-15 16:03:52 +02:00
cfd3ea61f1
pzsdr-to-pzsdr2
2016-11-14 14:12:22 -05:00
f64b44c8ac
sdrstk2pluto- contents
2016-11-11 13:52:57 -05:00
2ececad58c
sdrstk-2-pluto
2016-11-11 13:49:04 -05:00
c80033cb1b
util_fir_int: removed s_axis_data_tvalid and updated sdrstk
2016-11-11 17:52:19 +02:00
e62fe0c086
fmcjesdadc1- a5gt/a5soc- sysclk is different
2016-11-11 10:34:18 -05:00
7008c641b5
axi_adrv9371/zc706: Constraints update
...
From source *jesd_rstgen* is a false path for TX and RX_OS too.
2016-11-11 10:35:09 +02:00
85eac8c811
fmcjesdadc1/a5*- updates
2016-11-10 16:57:06 -05:00
959055bd54
common/a5gt- updates
2016-11-10 16:56:35 -05:00
7a2c713a4e
fmcjesdadc1/a5* - hdlmake.pl
2016-11-10 11:37:06 -05:00
c6730ab2d7
fmcjesdadc1/a5gt- updates
2016-11-10 11:36:41 -05:00
c207589f4b
fmcjesdadc1/a5gt - qsys2tcl flow
2016-11-10 11:32:29 -05:00
8af0731bb0
a5gt- qsys2tcl flow
2016-11-10 11:30:18 -05:00
7a606cbae1
sdrstk: Maximum clock frequency is 61.44 in CMOS mode
2016-11-10 17:45:35 +02:00
d29ef14f36
sdrstk: Configured ad9361 in 1r1t mode
2016-11-10 17:06:42 +02:00
a54092c9bb
fmcjesdadc1: Update projects to xcvr framework
...
This commit contains modifications for Xilinx only
2016-11-10 10:59:52 +02:00
d6918de19e
ad6676: Update projects to xcvr frame work
2016-11-10 10:39:46 +02:00
3cc416ca60
pzsdr1- fix typo on system_ps7
2016-11-09 12:04:30 -05:00
35c2dd5d6d
adrv9371x/zc706: Fix constraints
2016-11-09 16:34:08 +02:00
0b58a2a1db
avl_adxcvr- sysclk frequency
2016-11-09 09:21:07 -05:00
aef3e87d7e
fmcjesdadc1/a5soc -- xcvr frame work updates
2016-11-08 15:20:48 -05:00
53c2f0642b
fmcjesdadc1/a5soc -- xcvr frame work updates
2016-11-08 15:20:33 -05:00
f0af8216ce
common/a5soc- device can not run at 100M cpu clock
2016-11-08 15:19:23 -05:00
d9cfccc05f
common/a5soc- gpio in/out separation
2016-11-08 15:19:02 -05:00
acb9bf3902
hdlmake- a5soc/a5gt- updates
2016-11-04 15:02:57 -04:00
6b492b79db
a10soc - remove default assignments
2016-11-04 15:01:19 -04:00
8ea9beffaf
fmcjesdadc1- a5soc tcl updates
2016-11-04 15:01:19 -04:00
4e99c3be9a
a5soc- tcl flow updates
2016-11-04 15:01:19 -04:00
ce3b6a2d3f
adrv9371x: Updated constraints for altera projects
2016-11-04 18:20:46 +02:00
0dfbb0af11
arradio/c5soc- constraints changes- interface 1r1t
2016-11-03 11:25:52 -04:00
128ca7719a
ccpci_lvds- rev.d. xcvr pin changes
2016-11-02 16:41:04 -04:00
1cbea90bac
altera - a10gx bank swap
2016-11-01 12:41:25 -04:00
1e0fed82f7
alt_serdes- a10 ddio fixes
2016-11-01 12:41:25 -04:00
671a547c2b
hdlmake- updates
2016-11-01 12:41:25 -04:00
d010f3e687
sdrstk: Update Makefile to remove pack/cpack dependancy and add util_fir_dec/util_fir_int dependancy
2016-10-28 16:13:52 +03:00
ac8a6124af
sdrstk: Added interpolation and decimation filters. Removed cpack/upack
2016-10-27 19:33:28 +03:00
50552ce7d6
adrv9371x- altera updates
2016-10-27 09:25:00 -04:00
f752f0c9d7
a10soc- xcvr updates
2016-10-27 09:25:00 -04:00
d4c7b7ca57
ccusb_lvds: Fixed IIC constraints
2016-10-26 11:12:02 +03:00
6607aa707d
pzsdr1: Renamed projects to have lvds/cmos sufix
2016-10-26 11:09:43 +03:00
9ff92fdf5b
pzsdr: Renamed projects to have lvds/cmos sufix
2016-10-26 11:07:29 +03:00
b8363d778d
arradio: Makefile update
2016-10-25 20:36:56 +03:00
138eeebc9b
ccusb_lvds: Initial commit
2016-10-25 16:32:44 +03:00
5731ba3300
fmcomms11- xcvr updates
2016-10-24 09:51:40 -04:00
7e57a89ce5
daq1: Add support for A10GX
2016-10-24 11:43:33 +03:00
c9ac870086
usrpe31x- updates
2016-10-21 13:59:43 -04:00
7b958fed87
hdlmake- updates
2016-10-21 13:59:43 -04:00
48e90f0e9b
usrpe31x- added
2016-10-21 13:59:43 -04:00
801f980aeb
adrv9371: Fix parameter name
2016-10-21 12:50:20 +03:00
3abd87631a
fmcomms11: Fix parameter name
2016-10-21 12:49:48 +03:00
7db0c03a92
pzsdr1+ccbox -- updates
2016-10-19 10:32:28 -04:00
c1b7c5e77a
usb_fx3: Added FIFO on the FX3 to Zynq path, between FX3 core and DMA core
2016-10-19 09:30:51 +03:00
17cfdd6be9
fmcomms2/a10gx: Update Makefile and qsys script
2016-10-18 12:42:14 +03:00
918ce45e2a
pzsdr1/ccbox- updates
2016-10-17 16:29:57 -04:00
cb97bc500a
hdlmake updates
2016-10-17 16:29:57 -04:00
950acaed15
ccbox- copy
2016-10-17 16:29:57 -04:00
7c541c704a
usdrx1: ZC706, Update project to the new GT framework
2016-10-14 18:08:08 +03:00
1d1fe26624
fmcomms7: ZC706, Update project to new GT framework
2016-10-14 17:32:23 +03:00
5bb77109ca
daq2/a10gx- make fix
2016-10-10 13:03:44 -04:00
905e29eb01
hdlmake- altera
2016-10-10 12:55:55 -04:00
e5cf417576
daq2/mb- xcvr procedures
2016-10-10 12:51:30 -04:00
273073a584
daq2/kcu105- xcvr procedure
2016-10-10 11:12:47 -04:00
b3d3876dc5
imageon: ZC706, updated system_top to remove part of the Warnings.
...
- constraints fixed so Vivado doesn't issue a Warning
2016-10-10 17:33:42 +03:00
9efc45f0b6
imageon: Zed, updated system_top to remove part of the Warnings.
...
- spi csn signals should be tied to 1 if spi is not used
- constraints fixed so Vivado doesn't issue a Warning
2016-10-10 17:31:25 +03:00
8875c5bef3
fmcomms6: ZC706, updated system_top to remove part of the Warnings
2016-10-10 16:43:23 +03:00
fcd56a2f90
daq3/a10gx: Update project to the new GT framework
...
- Update common script
- Update system_top, some port names were changed
- Update constraint files
2016-10-10 16:22:08 +03:00
94f55f20e9
adv7511: KCU105, updated system_top to remove part of the Warnings
2016-10-10 16:12:17 +03:00
f464497062
cn0363: Microzed, updated system_top to remove part of the Warnings
2016-10-10 16:08:59 +03:00
2e605fc060
cn0363: Zed, update system_top to remove part of the Warnings
2016-10-10 15:56:46 +03:00
a12d34a98b
adv7511: Zed, updated system_top to remove part of the Warnings
2016-10-10 15:54:34 +03:00
c737afebf8
adv7511: KC705, updated system_top to remove part of the Warnings
2016-10-10 13:24:40 +03:00
74faac9210
ad9467_fmc: KC705, updated system_top to remove part of the Warnings
2016-10-10 13:19:55 +03:00
ffaf78665f
daq2- xcvr procedures
2016-10-06 14:44:20 -04:00
3b55822db3
daq2- xcvr connect
2016-10-06 14:09:27 -04:00
721ee98a06
zcu102- misc fixes
2016-10-06 10:18:14 -04:00
8965bcffb7
make: Update make files for DAQ3
2016-10-06 10:27:00 +03:00
9ace02a227
daq3/a10gx: Update project to the new GT framework
2016-10-06 10:25:25 +03:00
58c4abd8af
daq3/kcu105: Update project to the new GT framework
2016-10-06 10:23:52 +03:00
ca4dca87e2
daq2- updates
2016-10-05 14:02:59 -04:00
baabe20766
common/zcu102- spi connections & clock
2016-10-05 14:01:59 -04:00
bab9b2df0b
daq3/zc706: Update project with the new transceiver modules
2016-10-05 17:41:25 +03:00
c196b5bf68
ad6676evb: VC707, fixed system top gpio_bd datawidth
2016-10-05 15:50:43 +03:00
0208335ef3
hdlmake- updates
2016-09-30 13:20:22 -04:00
27c9bdddb6
daq2/zcu102- 2016.2 updates
2016-09-30 11:55:10 -04:00
8e1034946f
fmcomms2/zcu102- 2016.2 updates
2016-09-30 11:55:10 -04:00
9afff7ae60
common/zcu102- 2016.2 updates
2016-09-30 11:55:10 -04:00
33f9ed33c7
projects- ultrascale+
2016-09-30 11:55:10 -04:00
0ded52d8f6
daq2/zcu102- kcu105 copy
2016-09-30 11:55:10 -04:00
7290bcc81a
hdlmake- updates
2016-09-29 11:50:58 -04:00
4950c6c773
adrv9371x - xcvr updates
2016-09-29 11:50:58 -04:00
4a5b7fc723
scripts- reconnect added
2016-09-29 11:50:58 -04:00
e40311eee9
adrv9371x: A10soc, connected DMAs through 128 bit SDRAM0 port at 175MHz
2016-09-29 09:14:37 +01:00
4239f64125
dacfifo- board pin warnings
2016-09-27 14:49:20 -04:00
751a66eb72
plddr3/zc706- board pin warning
2016-09-26 15:20:37 -04:00
79b9e21be8
board- xcvr procedure
2016-09-26 15:20:18 -04:00
8314efd4e9
fmcomms11- xcvr updates
2016-09-26 15:19:29 -04:00
7fd9280cbf
fmcomms11- xcvr updates
2016-09-26 15:19:05 -04:00
f5809b8817
adrv9371x: a10soc, added adcfifos; connected the new reset to all peripherals; used the new f2sdram1 port
2016-09-24 10:09:05 +03:00
2d307d5f58
a10soc: Added system reset bridge. Using F2SDRAM port used in the previous Qsys design
2016-09-24 10:06:35 +03:00
df37a23a48
pzsdr/ccfmc- rgmii critical warnings fix
2016-09-22 11:38:43 -04:00
dc6f7bbc4e
pzsdr/ccfmc - loopback updates
2016-09-22 11:18:13 -04:00
0e2572bbd8
pzsdr- ccbrk_cmos- loopback changes
2016-09-21 13:16:04 -04:00
14ad1ea741
pzsdr- swap clear-up
2016-09-21 13:15:40 -04:00
21b5e9c634
hdlmake- updates
2016-09-21 11:56:03 -04:00
143423e3b9
adrv9371x: A10SOC, fix Makefile and system scripts to be compatible with altera
2016-09-21 18:13:02 +03:00
500d8bfb90
adrv9371x: A10GX, fix makefile and system_qsys.tcl script
2016-09-21 18:11:35 +03:00
79f34c9de7
ccbrk- test updates
2016-09-21 11:04:22 -04:00
a2e60cf693
ccbrk - test
2016-09-21 11:04:22 -04:00
3ca9fe0919
sdrstk- remove critical warnings from ps7
2016-09-16 14:06:12 -04:00
f1e787f86b
fmcomms2: TDD control is enabled by default
2016-09-16 14:45:39 +03:00
2a7bc31c01
pzsdr1- disable gpreg constraints
2016-09-15 13:49:04 -04:00
67d4e71ff0
pzsdr1- disable gpreg constraints
2016-09-15 12:41:40 -04:00
16ee1336c3
Makefile: Update make files
2016-09-15 11:41:06 +03:00
631923e9f0
usb_fx3: Update to Vivado 2016.2
2016-09-14 15:41:27 +03:00
9118ca3986
version_upgrade: Update MOTCON2 to 2016.2
2016-09-14 10:58:06 +03:00
cf9ac730a8
pzsdr1- new rev. board delays
2016-09-13 10:32:13 -04:00
9a2d2e8a02
version_upgrade: Update FMCADC4 to 2016.2
2016-09-13 15:04:11 +03:00
236a938425
daq2/a10gx- qsys updates
2016-09-12 14:57:50 -04:00
5df30ac6b0
daq2/a10gx- xcvr sharing
2016-09-12 14:57:50 -04:00
521c41ce32
adrv9371x: Updated a10soc project. Common design differentiates between nios and a10soc carrier
2016-09-08 11:44:45 +03:00
40c9fc92c1
a10soc: Switched to tcl flow
2016-09-08 11:31:06 +03:00
0d095f5da9
a10gx: Added system_type variable in common design
2016-09-08 11:29:14 +03:00
bae63ae5b1
version_upgrade: Update the DAQ3 project to 2016.2
2016-09-06 11:41:37 +03:00
b8c34791d5
version_upgrade: fmcjesdadc1 updated to 2016.2
...
Xilinx IP core JESD204 is updated to version 7.0
2016-09-06 11:41:37 +03:00
b837883b98
pzsdr1/pzsdr1/pzsdr1_cmos_system_constr: Fixed voltage level selection
2016-09-01 17:16:59 +03:00
93fa5aeec3
fmcadc2/vc707: Add adf4355 access, update design to Vivado 2016.2
2016-09-01 16:11:39 +03:00
dc21384002
pzsdr: Update ccpci base design
2016-09-01 09:06:30 +03:00
2f9ac4a342
altera- qsys-script does not support most tcl commands
2016-08-30 11:50:36 -04:00
917da79da1
altera- source defaults for qsys-script
2016-08-30 11:50:36 -04:00
8192e755e1
altera- defaults
2016-08-30 11:50:36 -04:00
1eccf5af07
fmcomms7: Update common design to Vivado 2016.2
2016-08-30 16:46:15 +03:00
2015bcedaa
fmcadc2: Update common design to Vivado 2016.2
2016-08-30 16:42:58 +03:00
6f0d124861
fmcadc5: Update to Vivado 2016.2
2016-08-30 16:09:28 +03:00
4248b9373a
ad6676evb: Update to Vivado 2016.2
2016-08-30 16:08:07 +03:00
a6e6b3f96e
version_upgrade: Update fmcomms1 common design to Vivado 2016.2
2016-08-29 15:59:15 +03:00
2e59f377e1
version_upgrade: Update ac701, mitx045 and zed common design to Vivado 2016.2
2016-08-29 09:50:46 +03:00
271029768c
pzsdr/cmos - swap==1
2016-08-26 10:31:00 -04:00
d18f6aa816
adrv9371x: A10GX, added adcfifo
...
- connected dac dma to 133 MHz clock
- set explicit clock rate to xcvr reference clock bridge
2016-08-26 14:46:48 +03:00
5cc2ab37a5
version_upgrade: Common ZC702 get an upgrade to 2016.2
...
Xilinx IP Clock Wizard updated to version 5.3
2016-08-26 10:20:04 +03:00
cd0c981b50
projects/scripts: Fix to prevent a warning
...
In case of axi_interconnects, when just one slave and master interface is
active, the 'Interconnect Optimization Strategy' is disabled. So this
parameter should be set just if there is more than one slave interface.
2016-08-26 10:08:00 +03:00
6ab137a0e9
projects/scripts: Cosmetics
2016-08-26 10:07:08 +03:00
9dfcfe6146
version_upgrade: adv7511 common script to 2016.2
...
Xilinx IP Clock Wizard updated to version 5.3
2016-08-26 09:52:01 +03:00
264bde77ad
sdrstk- SWAP==1 option
2016-08-24 12:07:13 -04:00
3c6cfdc7b5
adrv9371x: A10GX, switched TX lanes
2016-08-24 18:06:14 +03:00
215edb11c6
adrv9371: A10GX, updated design
...
- disable reconfiguration for RX transceivers and enabled the reconfiguration for TX transceiver. They cannot be enabled at the same time at this point
- update FIFO SIZE to 16 for all DMAs
- updated memory connections to 256 bit and moved clock connection to 133 MHz, for all DMAs.
2016-08-23 18:25:48 +03:00
320f87d63b
sdrstk- fix spi/port connections
2016-08-22 16:52:43 -04:00
270f8a6bbe
adrv9371x: Updated project common
2016-08-22 16:58:21 +03:00
Rejeesh Kutty
Adrian Costina
AndreiGrozav
Istvan Csomortani
Nick Pillitteri
Lars-Peter Clausen
István Csomortáni