Commit Graph

38 Commits (4307e3071f615ae9a604a1b490f0f9f3d7abc4fa)

Author SHA1 Message Date
Iacob_Liviu 482f0489a3 scripts: Merge adi_env.tcl into a single file
Move the new adi_env.tcl file from hdl/projects/scripts into hdl/scrips
2022-08-08 13:52:54 +03:00
Iulia Moldovan 961ebe0cc2 projects: Update .v files according to guideline
Deleted lines after endmodule and consecutive empty lines.
Modified parentheses, extra spaces.
Fixed indentation.
Fixed parameters list to be each parameter on its line.

Signed-off-by: Iulia Moldovan <iulia.moldovan@analog.com>
2022-06-28 18:06:56 +03:00
Adrian Costina d40db9e204 adrv9009zu11eg: Added additional GPIOs and CS to the GPIO expander
This should integrate seamlessly with SYNCHRONA14
2022-04-01 10:24:04 +03:00
Stanca Pop e22a597752 adrv2crr_fmcxmwbr1: Initial commit 2022-03-18 10:19:40 +02:00
Laszlo Nagy 8ec657315c adrv9009zu11eg: Drive cpack/upack reset from TPL 2022-02-07 19:14:01 +02:00
Laszlo Nagy d949936a1b adrv9009zu11eg/common: EXT_SYNC updates
- Explicitly enable EXT_SYNC parameter for Rx/Obs
- Loopback manual sync for each TPL  (we do not combine them yet because
  it requires extra CDC logic)
2022-02-07 19:14:01 +02:00
Filip Gherman 6dddaaaa78 adrv9009zu11eg/adrv2crr_xmicrowave: Update Makefile 2021-12-22 11:33:15 +02:00
Stanca Pop 0d45f4dc94 xmicrowave: Fix typo 2021-12-17 15:44:23 +02:00
PopPaul2021 c71e5de928
zcu102: ad_fmclidar1_ebz, fmcomms5, fmcomms8 (#811)
adrv2crr_fmc: adrv9009zu11eg
adrv2crr_xmicrowave: adrv9009zu11eg

The IBUFGDS primitive is deprecated in UltraScale devices.
2021-11-22 08:09:46 +02:00
Laszlo Nagy fe58a5fb47 adrv9009zu11eg/adrv2crr_fmcomms8: Add clock buffers for core clocks
The IBUFGDS primitive is deprecated in UltraScale devices.

Signed-off-by: Laszlo Nagy <laszlo.nagy@analog.com>
2021-11-11 17:33:10 +02:00
Robin Getz 63b6711cfa start adding some doc to the ./projects directory
This adds a Readme.md to each project directory with pointers to project
documentation in the wiki, and the drivers (if they exist). This will
help with some autogenerated doc in the wiki, that is generated with the
innovatily named "wiki_summary.sh" shell script that parses through
these Readme.md files, and generates a summary table.

Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Iacob Liviu Mihai <liviu.iacob@analog.com>
2021-11-10 14:01:06 +02:00
Stanca Pop bcf5abb2fe xmicrowave: Initial commit 2021-11-02 15:44:47 +02:00
Adrian Costina 591a23156b Makefiles: Update header with the appropriate license 2021-09-16 16:50:53 +03:00
Laszlo Nagy b7f34f7bd9 adrv9009zu11eg & common/zcu102 : Fix zynqmp ref clock definition
The derived clocks of the zynqmp core are not calculated correctly due
rounding issues, instead of 100MHz the value of 99999001 is received
causing warnings during system validation.

This can be fixed/worked around with the proper reference clock
definition.
2021-08-20 10:46:09 +03:00
Adrian Costina 4cf53f373b Revert "adrv9009zu11eg: Integrate data_offload"
This reverts commit 78999e154e.
The integration wasn't properly tested
2021-08-19 21:43:09 +03:00
Istvan Csomortani 78999e154e adrv9009zu11eg: Integrate data_offload 2021-08-06 11:55:24 +03:00
Sergiu Arpadi 40baa63f0f adrv2crr_fmcomms8: Fix system_top.v 2021-03-19 17:56:28 +02:00
Sergiu Arpadi a1773c661c adrv9009zu11eg_crr: Update spi
Add two more CS signals to P25 connector
2021-03-10 10:53:11 +02:00
Adrian Costina 7be66b63c1 adrv9009zu11eg:fmcomms8: Fix lane swapping for TX channels 0 and 1 on the FMCOMMS8 2021-02-05 15:07:09 +02:00
Sergiu Arpadi 6f2f2b8626 makefile: Regenerate make files 2021-01-20 01:02:56 +02:00
sergiu arpadi acbbd4636a sysid: Upgrade framework, header/ip are now at 2/1.1.a
Unify tcl scripts; rename adi_pd_intel.tcl to adi_pd.tcl
add git branch to internal use area; update log prints;
update xilixn projects; fix cn0506 sysid script;
2021-01-20 01:02:56 +02:00
Istvan Csomortani e41ba7f6f5 adrv9009zu11eg: Use adi_project_create instead of adi_project 2021-01-15 15:26:43 +02:00
Istvan Csomortani 2799777657 adrv9009zu11eg/adrv2crr_fmc: Fix hmc7044_car_gpio connections 2020-11-11 07:07:29 -05:00
Adrian Costina ecd880d44c adrv9009zu11eg:fmcomms8: Fix SPI timing constraint 2020-11-05 17:42:41 +02:00
Adrian Costina ae7ec82334 adrv9009zu11eg: Update spi module to use generic verilog 2020-11-02 16:13:35 +02:00
Adrian Costina 9093a8c428 library: Move ad_iobuf to the common library, as it's not Xilinx specific
Updated all system_project and Makefiles
2020-11-02 16:13:35 +02:00
Adrian Costina 9364c8501a adrv9009_zu11eg: Add synchronization at application layer
Switch RX path reset to be controlled by the TPL and use
RX SYSREF as external synchronization for the ADC TPL
Use TX SYSREF for synchornizing the TX DDS
2020-10-07 09:04:21 +03:00
Sergiu Arpadi d8ab27b2af sysid: Remove cstring init string 2020-09-30 19:12:24 +03:00
Adrian Costina c4b94fc564 adrv9009zu11eg: Add S JESD204 parameter for the projects 2020-02-18 11:19:02 +02:00
Adrian Costina 645696e5b4 adrv9009zu11eg: Extend SPI connection to the PL HD PINS expansion 2020-02-18 11:19:02 +02:00
Adrian Costina d2817863a1 adrv9009zu11eg: Add FMCOMMS8 support 2020-02-18 11:19:02 +02:00
Adrian Costina 29f18e501e adrv9009zu11eg: Cleanup bd file 2020-02-18 11:19:02 +02:00
Arpadi 74fc68d4c3 axi_fan_control: Changed temperature thresholds to registers
implemented mux for temp reading either from internal or external
source; updated regmap; added param to identify source for temp
information; updated tacho measurements; added AVG_POW param used
for tacho measuremet average useful for simulations; defaults for
tacho measurements changed to params and added registers; added
prescaler for fsm control, FSM updated; changed register write
process; connected INTERNAL_SYSMONE to regmap, value can now be
read by software;
2020-02-14 11:21:12 +02:00
Adrian Costina 09ad67bfd7 adrv9009zu11eg: Make the project more parametrizable 2019-12-04 14:59:18 +02:00
Adrian Costina 0cb5c0bdaf adv9009zu11eg: Update FPGA to -2. Update DDR4 clock frequency 2019-11-27 16:27:44 +02:00
Adrian Costina dfe3258a4f adrv9009zu11eg: Add axi_sysid 2019-11-19 10:29:57 +02:00
Adrian Costina 81d3a9eb66 adrv9009zu11eg: Reduce SPI Clock speed to meet timing 2019-11-19 10:29:57 +02:00
Adrian Costina a589a2c7eb adrv9009_zu11eg_som: Change design partitioning
Create a structure similar with ADRV936x projects
2019-11-14 15:25:23 +02:00