4307e3071f
scripts:adi_env: Change the default version of Quartus Pro to 21.4 ( #988 )
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New version of Quartus Pro for A10SOC, A10GX and S10SOC was changed
to 21.4. Is known that some projects will not build anymore due to
timming violations.
2022-08-18 17:08:29 +03:00
dde37124a4
scripts: Update Vivado version to 2021.2
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Signed-off-by: Iulia Moldovan <iulia.moldovan@analog.com>
2022-08-18 15:41:58 +03:00
0595f93452
AD777x support for ZedBoard and DE10Nano ( #937 )
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* library/common: Ad adc_status_header, adc_crc_err and adc_crc_enable.
* library/axi_ad777x: Initial commit for Xilinx and Intel
* projects/ad777x_ardz: Initial commit for ZedBoard and DE10Nano
2022-08-10 11:29:05 +03:00
482f0489a3
scripts: Merge adi_env.tcl into a single file
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Move the new adi_env.tcl file from hdl/projects/scripts into hdl/scrips
2022-08-08 13:52:54 +03:00
d48b1bcdce
ad9081_fmca_ebz/vck190: Expose ref clock parameter
2022-08-04 09:52:57 +03:00
78333b2c90
ad9081_fmca_ebz/common/versal_transceiver: Separate lane rates for Tx and Rx
2022-08-04 09:52:57 +03:00
3379dd3bdb
ad9082_fmca_ebz/zcu102: Make JESD_MODE overwritable
2022-08-04 09:50:18 +03:00
54a22d036c
adi_pd.tcl: Fix git_clean_string logic
2022-08-02 17:11:49 +03:00
94c4a291a7
cn0561_coraz7s: Fix gpio connections
2022-08-02 17:11:19 +03:00
bb3027995a
sysid: Add sysid support for de10nano
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make adv7513
make 0540
2022-08-02 14:15:34 +03:00
c748b3bbc7
ad9082_fmca_ebz/zc706: Fix parameters
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Match default parameters for L=4 M=8 mode with 10Gbps.
The L=8 M=4 would require lane rate of 15Gbps that is not supported on
zc706.
2022-08-01 16:40:03 +03:00
aae7971689
ad9082_fmca_ebz/vcu118: Fix default lane rate parameter
2022-08-01 16:40:03 +03:00
aed7032e0c
ad9082_fmca_ebz/zcu102: Fix default lane rate parameter
2022-08-01 16:40:03 +03:00
2b274f945f
ad9081_fmca_ebz: Reset cpack with Rx data offload
2022-08-01 12:47:26 +03:00
d48ab915a5
vcu128: Connect sys_mb_rstgen/ext_reset_in accordingly
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Signed-off-by: Filip Gherman <Filip.Gherman@analog.com>
2022-07-29 20:05:08 +03:00
6aa899f161
scripts/adi_project_xilinx.tcl: Add new constraints file support
2022-07-20 14:36:04 +03:00
9864d96096
Merge CN0506 projects into a parameterized one
2022-07-20 14:36:04 +03:00
961ebe0cc2
projects: Update .v files according to guideline
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Deleted lines after endmodule and consecutive empty lines.
Modified parentheses, extra spaces.
Fixed indentation.
Fixed parameters list to be each parameter on its line.
Signed-off-by: Iulia Moldovan <iulia.moldovan@analog.com>
2022-06-28 18:06:56 +03:00
171daab8f2
ad9081_fmca_ebz: a10soc: Update resistor change comment
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A board rework is required so the clocks, chip selects or sync signal reach the part correctly. Without this the link will not come up.
2022-06-21 14:19:58 +03:00
a8174ac038
ad_quadmxfe1_ebz/vcu118/system_project.tcl: Update comments
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Update PLL selection docs.
2022-06-08 15:35:47 +03:00
6525a37375
ad_fmclidar1_ebz:a10soc Fixed problems with SPI communication with AD9094 ( #951 )
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Now CPH and CPOL are set to 1, also the SPI clock is set to 10MHz
Signed-off-by: Liviu Adace <liviu.adace@analog.com>
2022-06-06 13:00:45 +03:00
4f4825a3df
projects:daq2:common: fix adi_tpl_jesd204_rx_create error. ( #952 )
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(\ character has to be removed or a blank line inserted before ad_ip_parameter)
Fix for : 0b8585a6f
2022-06-06 08:53:07 +03:00
0b8585a6f1
PN mismatch DAQ2, DAQ3 and FMCJESDADC1 fix ( #950 )
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The AD9680 is a dual 14-bit ADC.
Software sets the output format to offset binary before performing the PN tests.
2022-06-02 14:09:36 +03:00
f957d81db1
ad9083_evb_bd: Connect util_ad9083_rx_cpack reset to adc_rst
2022-05-27 09:20:09 +03:00
1ae375f4fb
ad_quadmxfe1_ebz/vcu118: Change drp clock source used for jesd204_phy
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- Added an utility buffer in order to generate the 50Mhz DRP clock.
- 'addn_ui_clockout4' will be used to generate the higher frequency 'sys_mb' clock for Microblaze.
Signed-off-by: Filip Gherman <Filip.Gherman@analog.com>
2022-05-27 00:48:34 +03:00
5ad9dfd6c0
vcu118: Increase Microblaze performance and clock frequency
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Increased the Microblaze performance for the VCU118 carrier:
- Increased the size of Instruction Cache and Data Cache to 64kB
Increased the Microblaze clock frequency:
- Using the DDR4 Controller to generate a new sys_mb_clk of 214 MHz to drive all the Microblaze interfaces at higher frequencies
Signed-off-by: Filip Gherman <Filip.Gherman@analog.com>
2022-05-27 00:48:17 +03:00
bdd5686e95
ad9081_fmca_ebz/a10soc: Make second sync CMOS and GPIO controllable
2022-05-26 09:13:05 +03:00
a2da965391
ad9081_fmca_ebz/vck190: Make second sync CMOS and GPIO controllable
2022-05-26 09:13:05 +03:00
20b89ddd99
ad9081_fmca_ebz/vcu128: Make second sync CMOS and GPIO controllable
2022-05-26 09:13:05 +03:00
b3d231e569
ad9081_fmca_ebz/zc706: Make second sync CMOS and GPIO controllable
2022-05-26 09:13:05 +03:00
ab5c344c89
ad_fmclidar1_ebz:a10soc Fixed SPI communication on Arria 10 ( #947 )
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Signed-off-by: Liviu Adace <liviu.adace@analog.com>
2022-05-24 12:44:03 +03:00
08a5e944f0
cn0577: Initial commit
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Created a virtual clock to constrain cnv_en.
Given that the cnv_en should be asserted only once per 8 clock
cycles and only the rise edge is of interest, we can constrain
the path as multicycle path.
2022-05-18 18:23:38 +03:00
0c3ec108aa
ad9213_dual_ebz: Add possibility to change order of channels through a GPIO
2022-05-17 15:27:39 +03:00
496b4ec748
ad9213_dual_ebz: Fix constraints
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- added sysref constraint
- remove false path from the GPIO pins
2022-05-17 15:27:39 +03:00
ef377e58be
ad9083_evb_bd: make the project more generic
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Allow external parameters and a more flexible configuration.
2022-05-12 16:11:17 +03:00
69839ec327
ad_quadmxfe1_ebz: Refactor MxFE GPIOs
2022-05-11 18:09:08 +03:00
044017e0b9
ad9081_fmca_ebz/zcu102: Make second sync CMOS and GPIO controllable
2022-05-11 18:09:08 +03:00
e71dbbd6f9
cn0561_zed: Initial commit
2022-05-11 17:30:26 +03:00
0ac49027bd
cn0561_coraz7s: Initial commit
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Because the inferface signals which pass through the eval board's
Arduino connector are connected to level shifters the design
will not work at the maximum clk frequency of 48MHz. The maximum
tested frequency is 24MHz.
2022-05-11 17:30:26 +03:00
1ef3ff05ba
vcu128: Increase Microblaze performance and clock frequency
2022-05-11 13:20:01 +03:00
0ae2a17474
scripts/adi_board.tcl: Support connecting HPCx
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Support connecting HPC0 and HPC1 on PS8.
Co-authored-by: Mathias Tausen <mta@satlab.com>
2022-05-10 11:50:55 +03:00
53a95840c0
ad_quadmxfe1_ebz_bd: Bugfix for JESD configurations with less lanes
2022-05-09 10:43:31 +03:00
8f22985880
projects/scripts/adi_board: Add support for sparse channel maping
2022-05-09 10:43:14 +03:00
619e8043d0
Adaq8092 on ZedBoard LVDS output mode ( #921 )
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* common/up_adc_common: Add adc_custom_control register
* library/axi_adaq8092: Initial commit
* projects/adaq8092_fmc: Initial commit for ZedBoard
2022-04-28 15:39:59 +03:00
97b92565b2
Makefile: Replace util_fifo2axi_bridge with util_hbm
2022-04-28 14:31:32 +03:00
0e55583a63
daq2: Do not set AXI address width for DO
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Address size and memory ranges are automatically computed by the
external storage interfacing IP (util_hbm) based on the storage size and
base address so this parameter is redundant.
2022-04-28 14:31:32 +03:00
5a33c44511
daq2/zc706: Update to new DO storage
2022-04-28 14:31:32 +03:00
fa168fafe0
ad9081_fmca_ebz:vcu128: Disable offload bypass
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The internal bypass FIFO has poor timing performance,
when using HBM data can be passed always through the external memory
without storage length constraints, so no need for the internal bypass FIFO.
2022-04-28 14:31:32 +03:00
c57015f80e
ad9081_fmca_ebz/vcu128: Use HBM for data offload cores
2022-04-28 14:31:32 +03:00
dbadb9eb61
ad9081_fmca_ebz/common: Make data offload memory type selectable
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Make the storage type over writable so it can be set specifically
to carriers.
Address width of external memory AXI master is calculated in the
interfacing core (util_hbm) so that parameters is removed.
2022-04-28 14:31:32 +03:00
ladace
Iulia Moldovan
PopPaul2021
Iacob_Liviu
Laszlo Nagy
Laszlo Nagy
Sergiu Arpadi
Filip Gherman
alin724
Ionut Podgoreanu
Adrian Costina
AndreiGrozav
Stanca Pop
Morten Jensen