019390f9bf
block_design: Updates with new reset net variables
2019-06-11 18:13:06 +03:00
7960b00684
block_design: Update with new clock net variables
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Using the new clock net variables in all Xilinx block designs.
2019-06-11 18:13:06 +03:00
ce04f46b80
motcon2_zed: Fix timing problems
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-change implementation strategy
-axi_dmac add extra registers AXI_SLICE_SRC
This was done to increase the overall timing margin.
2019-02-12 10:43:46 +02:00
bf50916a3f
motocon: Use new pack infrastructure
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Use the new util_cpack2 and util_upack2 cores. They have lower utilization
that the old util_cpack and util_upack cores.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-11-28 11:33:11 +02:00
2f4904e4d2
motcon2_fmc: Remove muxaddr_out, refclk and refclk_rst from system_bd
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- refclk and refclk_rst were used for ethernet IDELAY, but are not needed anymore
- muxaddr_out pins overlap with regular GPIOs in the Zed base design. The XADC mux GPIOs can be controlled through that. Cusomters that want to directly control the pins through XADC IP must modify the design
2018-09-05 15:12:51 +03:00
5b222dba02
motcon2_fmc: Connect GPO pins to controller 1
2018-06-14 16:06:38 +03:00
e2df6b75c2
motcon2_fmc: Sync transfer start for the current monitor DMAs
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There are a maximum of 3 channels enabled for the path, sync start is required
2018-06-14 16:06:24 +03:00
091bbfa2d3
motcon2_fmc: Ethernet MDIO set to EMIO
2018-06-14 16:06:17 +03:00
12930c8470
motcon2_fmc: Explicitly assign ETH0 MDIO to EMIO
2017-05-22 18:53:00 +03:00
24b797f1a6
motcon2: ip automatic version update
2017-04-14 17:11:08 +03:00
d5165ca81f
motcon_fmc: Tie unused pins to GND
2016-12-13 19:20:13 +02:00
9118ca3986
version_upgrade: Update MOTCON2 to 2016.2
2016-09-14 10:58:06 +03:00
7c2f34549b
motcon2_fmc: Update common design to 2015.4
2016-03-23 10:27:07 +02:00
7013b319b0
motcon2_fmc: Fixed reset connection for cpack cores
2015-12-22 12:03:34 +02:00
83fb5c742a
motcon2_fmc: Updated project to Vivado 2015.2.1
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- added cpack cores
- removed controller DMA paths
2015-10-09 13:56:41 +03:00
275830d2b1
motcon2_fmc: Drop explicit axi_dmac clock synchronicity configuration
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The axi_dmac core is now capable of detecting whether its different parts
run in different clock domains or not. No need to configure it manually any
more.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-18 15:28:17 +02:00
d52308f074
axi_dmac: Change parameter name 2D_TRANSFER
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Parameter name can't start with numbers, 2D_TRANSFER was changed to DMA_2D_TRANSFER
2015-08-20 10:14:22 +03:00
57cfb7cfb1
hdl/library: Update the IP parameters
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The following IP parameters were renamed:
PCORE_ID --> ID
PCORE_DEVTYPE --> DEVICE_TYPE
PCORE_IODELAY_GROUP --> IO_DELAY_GROUP
CH_DW --> CHANNEL_DATA_WIDTH
CH_CNT --> NUM_OF_CHANNELS
PCORE_BUFTYPE --> DEVICE_TYPE
PCORE_ADC_DP_DISABLE --> ADC_DATAPATH_DISABLE
CHID --> CHANNEL_ID
PCORE_DEVICE_TYPE --> DEVICE_TYPE
PCORE_MMCM_BUFIO_N --> MMCM_BUFIO_N
PCORE_SERDES_DDR_N --> SERDES_DDR_N
PCORE_DAC_DP_DISABLE --> DAC_DATAPATH_DISABLE
DP_DISABLE --> DATAPATH_DISABLE
PCORE_DAC_IODELAY_ENABLE --> DAC_IODELAY_ENABLE
C_BIG_ENDIAN --> BIG_ENDIAN
C_M_DATA_WIDTH --> MASTER_DATA_WIDTH
C_S_DATA_WIDTH --> SLAVE_DATA_WIDTH
NUM_CHANNELS --> NUM_OF_CHANNELS
CHANNELS --> NUM_OF_CHANNELS
PCORE_4L_2L_N -->QUAD_OR_DUAL_N
C_ADDRESS_WIDTH --> ADDRESS_WIDTH
C_DATA_WIDTH --> DATA_WIDTH
C_CLKS_ASYNC --> CLKS_ASYNC
PCORE_QUAD_DUAL_N --> QUAD_DUAL_N
NUM_CS --> NUM_OF_CS
PCORE_DAC_CHANNEL_ID --> DAC_CHANNEL_ID
PCORE_ADC_CHANNEL_ID --> ADC_CHANNEL_ID
PCORE_CLK0_DIV --> CLK0_DIV
PCORE_CLK1_DIV --> CLK1_DIV
PCORE_CLKIN_PERIOD --> CLKIN_PERIOD
PCORE_VCO_DIV --> VCO_DIV
PCORE_Cr_Cb_N --> CR_CB_N
PCORE_VCO_MUL --> VCO_MUL
PCORE_EMBEDDED_SYNC --> EMBEDDED_SYNC
PCORE_AXI_ID_WIDTH --> AXI_ID_WIDTH
PCORE_ADDR_WIDTH --> ADDRESS_WIDTH
DADATA_WIDTH --> DATA_WIDTH
NUM_OF_NUM_OF_CHANNEL --> NUM_OF_CHANNELS
DEBOUNCER_LEN --> DEBOUNCER_LENGTH
ADDR_WIDTH --> ADDRESS_WIDTH
C_S_AXIS_REGISTERED --> S_AXIS_REGISTERED
Cr_Cb_N --> CR_CB_N
ADDATA_WIDTH --> ADC_DATA_WIDTH
BUFTYPE --> DEVICE_TYPE
NUM_BITS --> NUM_OF_BITS
WIDTH_A --> A_DATA_WIDTH
WIDTH_B --> B_DATA_WIDTH
CH_OCNT --> NUM_OF_CHANNELS_O
M_CNT --> NUM_OF_CHANNELS_M
P_CNT --> NUM_OF_CHANNELS_P
CH_ICNT --> NUM_OF_CHANNELS_I
CH_MCNT --> NUM_OF_CHANNELS_M
4L_2L_N --> QUAD_OR_DUAL_N
SPI_CLK_ASYNC --> ASYNC_SPI_CLK
MMCM_BUFIO_N --> MMCM_OR_BUFIO_N
SERDES_DDR_N --> SERDES_OR_DDR_N
CLK_ASYNC --> ASYNC_CLK
CLKS_ASYNC --> ASYNC_CLK
SERDES --> SERDES_OR_DDR_N
GTH_GTX_N --> GTH_OR_GTX_N
IF_TYPE --> DDR_OR_SDR_N
PARALLEL_WIDTH --> DATA_WIDTH
ADD_SUB --> ADD_OR_SUB_N
A_WIDTH --> A_DATA_WIDTH
CONST_VALUE --> B_DATA_VALUE
IO_BASEADDR --> BASE_ADDRESS
IO_WIDTH --> DATA_WIDTH
QUAD_DUAL_N --> QUAD_OR_DUAL_N
AXI_ADDRLIMIT --> AXI_ADDRESS_LIMIT
ADDRESS_A_DATA_WIDTH --> A_ADDRESS_WIDTH
ADDRESS_B_DATA_WIDTH --> B_ADDRESS_WIDTH
MODE_OF_ENABLE --> CONTROL_TYPE
CONTROL_TYPE --> LEVEL_OR_PULSE_N
IQSEL --> Q_OR_I_N
MMCM --> MMCM_OR_BUFR_N
2015-08-19 14:11:47 +03:00
2e46bda916
motcon2_fmc: Update project to use the latest util_gmii_to_rgmii
2015-06-16 17:43:10 +03:00
fbfbfdaf87
motcon2_fmc: Updated to the latest framework
2015-04-01 11:45:01 +03:00
f6df66ea06
motcon2_fmc: initial commit of the base design
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Because vivado crashes when adding the speed detector, it's not part of this commit.
The controller is also not part of this commit
2015-01-08 11:57:22 +02:00
Istvan Csomortani
AndreiGrozav
Lars-Peter Clausen
Adrian Costina