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10 Commits (43f460e7444a676dff7fa1d43473c775f4d3496f)

Author SHA1 Message Date
Laszlo Nagy fe2b43ddd9 base:constraint: Setting Configuration Bank Voltage Select 
Set the properties to mirror the hardware configuration so
the Vivado tools can provide warnings if there are any conflicts
between configuration pin settings, such as an IOSTANDARD
on a multi-function configuration pin that conflicts with the
configuration voltage.
see:
https://www.xilinx.com/support/documentation/user_guides/ug570-ultrascale-configuration.pdf

The following base constraints were updated:
 - kcu105
 - kc705
 - vc707
 - ac701
 2018-04-11 15:09:54 +03:00
Lars-Peter Clausen 6862655b0d Add .gitattributes file 
Add .gitattributes file which sets up the eol encoding handling. This will
make sure that we get a uniform eol encoding across different operating
systems.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2015-06-26 11:07:10 +02:00
Adrian Costina 8ed301a264 AC701: Common, removed system clock constraint 2015-04-02 11:51:20 +03:00
Istvan Csomortani c00633d1ac adv7511_ac701: Update project and common files to the new framework. 2015-03-30 15:23:26 +03:00
Adrian Costina 05ed98f884 common: Updated common constratins for ac701, kc705, vc707, zc702 2014-11-11 12:35:44 +02:00
Lars-Peter Clausen 50faf0c53a Remove executable flags from non-exectuable files 2014-09-09 15:05:06 +02:00
Adrian Costina a881557645 base_design: Fixed AC701 and VC707 contstraints 
AC701: Modified the IOSTANDARD for some of the pins to correspond to the
AC701 user guide.
VC707: Fixed naming for some system clocks
 2014-03-31 17:38:20 +03:00
Istvan Csomortani 3a0d1282b7 Fix the remaining issues 
- Swap the IO locations of ports vsync and hsync
	- Change the mem_interconnect optimization strategy to Maximize
	  Performance
 2014-03-20 14:36:01 +02:00
Rejeesh Kutty 5c3b65d01b adv7511: kc705/ac701 updates 2014-03-06 09:36:50 -05:00
Rejeesh Kutty 360f10395a initial checkin 2014-03-03 13:42:25 -05:00