Commit Graph

2317 Commits (44568f1f6452d324c2be41dd2f31d54da8f357d4)

Author SHA1 Message Date
Adrian Costina 46808c4c41 util_wfifo: Changed some reset for several registers from asynchronous to synchronous for better integration with the FIFO 2015-09-16 18:55:47 +03:00
Adrian Costina 70cea5b14e fmcomms1: Removed ILA 2015-09-16 18:51:40 +03:00
Adrian Costina 6804f3377a axi_ad9643: Updated core with latest constraints 2015-09-16 15:49:13 +03:00
Adrian Costina 5347c058df axi_ad9122: Updated core with latest constraints 2015-09-16 15:48:33 +03:00
Adrian Costina 884f45c81d common library: Registered dc_filter and iq_correction coefficients 2015-09-16 14:24:18 +03:00
Adrian Costina 67ffeb18e8 axi_ad9739a: Updated core with latest constraints 2015-09-11 14:04:33 +03:00
Adrian Costina 63aaa58861 ad9265_fmc: Updated project, removed ILA related clocks 2015-09-11 11:27:58 +03:00
Adrian Costina e33403816c axi_ad9265: Updated core with latest constraints 2015-09-11 11:26:28 +03:00
Istvan Csomortani 5bc16159fa ad_tdd_sync: The resync will reset all the control lines 2015-09-10 11:28:36 +03:00
Istvan Csomortani a679251d7d Makefiles: Update Make 2015-09-09 17:13:19 +03:00
Istvan Csomortani f3eca48533 pzsdr_rfsom: Update project with the new TDD sync interface 2015-09-09 12:37:52 +03:00
Istvan Csomortani 510f1cfdd9 fmcomms2_zc706: Update project with the new TDD sync interface 2015-09-09 12:35:22 +03:00
Istvan Csomortani 85ffc25ec5 ad_tdd_sync: Update the synchronization logic
The synchronization interface is a single bidirectional line. Output for Master, input for Slave.
The sync_period value is relative to frame length and the digital interface clock. The actual synchronization
period will be: sync_period * frame_length * fb_clock_cycle
2015-09-09 12:31:58 +03:00
Istvan Csomortani 5a566b9e5d ad_tdd_control: Add delay compensation for the control lines 2015-09-09 12:24:26 +03:00
Istvan Csomortani 6acb350ee5 axi_dmac: Update for axi_dmac_constr.xdc
Parameter called 'processing_order' default value is 'late'. No need to specify it at process call.
2015-09-09 12:08:35 +03:00
Rejeesh Kutty 381ffd43c1 gtlb- remove pn test-reset 2015-09-08 13:52:33 -04:00
Adrian Costina f428d8bde9 adv7511: KC705, updated design so that the axi_hdmi_dma core has memory connection datawidth of 512 2015-09-08 16:43:40 +03:00
Adrian Costina d81d8238a9 kc705: Updated mig project file 2015-09-08 16:42:23 +03:00
Adrian Costina 2757cd8baf adv7511: AC701 fixed system top 2015-09-07 16:48:10 +03:00
Rejeesh Kutty 214f5b18c1 no-trace option 2015-09-03 16:16:31 -04:00
Rejeesh Kutty 00a55ded00 ibert to jesd-gt change 2015-09-03 16:16:30 -04:00
Rejeesh Kutty 77ee3c4cbc ibert to jesd-gt change 2015-09-03 16:16:28 -04:00
Rejeesh Kutty dbf7c154b2 no-trace option 2015-09-03 16:16:27 -04:00
Rejeesh Kutty e2aca435e5 ibert-to-jesd-gt change 2015-09-03 16:16:25 -04:00
Rejeesh Kutty 9bef9742b7 jesd_gt- cosmetic changes 2015-09-03 16:16:24 -04:00
Rejeesh Kutty 84ced344d9 gtlb- up-sync make w1c 2015-09-03 16:16:22 -04:00
Rejeesh Kutty f1d416a98b daq2/a10gx- ethernet fix 2015-09-02 14:31:15 -04:00
Rejeesh Kutty 1fff1076b1 daq2/a10gx- ethernet fix 2015-09-02 14:31:15 -04:00
Rejeesh Kutty 01c0fdc809 daq2/a10gx- ethernet fix 2015-09-02 14:31:15 -04:00
Istvan Csomortani 1ecd615f92 common/mitx045 : Fix the vdma interface of axi_hdmi_core 2015-09-02 16:33:30 +03:00
Lars-Peter Clausen 9fb336e464 usdrx1: Add DDR FIFO
The converters on the usdrx1 generate 2.5GB/s. This more than we can
transport over the HP interconnects to the system memory.

Add a dedicated DDR FIFO to design which can be used to buffer the data
before it is transferred to the main memory.

Also increase the interconnect clock rate from 100MHz to 200MHz and the DMA
FIFO size from 4 to 8, so we can transfer the captured data faster to the
main memory.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-01 11:29:36 +02:00
Lars-Peter Clausen bbada6ed8f usdrx1: Add overflow flag to ILA
It's useful to know if and when a overflow happens.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-01 11:29:36 +02:00
Lars-Peter Clausen c67aecc1eb usdrx1: Disable SYNC_TRANSFER_START for the DMA
There is no sync signal in this design, so the flag needs to be set to 0.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-01 11:29:36 +02:00
Lars-Peter Clausen e0b5044aa3 axi_dmac: Disable dummy AXI ports for Xilinx IPI
The memory mapped AXI interfaces for the AXI-DMAC are uni-directional.
Which means they are either write-only or read-only. Unfortunately the
Altera tools can't handle this, so we had to add dummy signals for the
other direction.

The Xilinx tools on the other hand handle uni-directional AXI interfaces
and in fact IPI can do a better job and use less resources when creating
the AXI interconnects when it knows that the interface is uni-directional.
So always disable the dummy ports for the IPI package.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-01 11:29:36 +02:00
Rejeesh Kutty 9b37d6bfe7 pzslb- updates - wip 2015-08-31 15:41:29 -04:00
Rejeesh Kutty 2a09257f38 pzslb- updates - wip 2015-08-31 15:41:28 -04:00
Rejeesh Kutty 49430dc2b0 pzslb- copy 2015-08-31 15:41:27 -04:00
Rejeesh Kutty 879a75a690 pzslb- copy 2015-08-31 15:41:26 -04:00
Rejeesh Kutty fdc3dbb805 pzslb- copy 2015-08-31 15:41:25 -04:00
Rejeesh Kutty fc79af6edc pzslb- common 2015-08-31 15:41:24 -04:00
Rejeesh Kutty f005de9ee2 pzslb- added 2015-08-31 15:41:23 -04:00
Rejeesh Kutty c1b01517f8 util_gtlb: added 2015-08-31 15:41:22 -04:00
Rejeesh Kutty a67ae238f8 rfsom-ps7- ddr settings 2015-08-31 15:39:45 -04:00
Rejeesh Kutty 212235189f hdmi-tx- signal name changes 2015-08-28 13:48:33 -04:00
Rejeesh Kutty 0e20277bc1 hdmi-tx- signal name changes 2015-08-28 13:48:33 -04:00
Rejeesh Kutty 93fe70790d hdmi-tx- signal name changes 2015-08-28 13:48:33 -04:00
Rejeesh Kutty 810fced1ec hdmi-tx- signal name changes 2015-08-28 13:48:33 -04:00
Rejeesh Kutty 01852a14de hdmi-tx- signal name changes 2015-08-28 13:48:33 -04:00
Rejeesh Kutty 1e5afdd535 axi_hdmi_tx- altera ip changes 2015-08-28 13:48:33 -04:00
Rejeesh Kutty 6cf7eb5ad4 axi_hdmi_tx- altera ip changes 2015-08-28 13:48:33 -04:00