Commit Graph

6 Commits (457c5f7d86fb14084be935dd9bb92da29b612236)

Author SHA1 Message Date
Adrian Costina c32b4b02f3 sync_bits: Change I/O names of wires "in" and "out" for VHDL users 2019-04-23 18:03:23 +03:00
Lars-Peter Clausen d72fac4b1e Add missing timescale annotations
For consistent simulation behavior it is recommended to annotate all source
files with a timescale. Add it to those where it is currently missing.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-10-17 10:32:47 +03:00
Lars-Peter Clausen 965d3b4c79 util_cdc: Silence warnings about unused sequential logic
Some parts of the util_cdc library rely on dead logic elimination to remove
unused logic. Unfortunately with newer Vivado versions this results in
warnings about unused sequential elements being removed. Like:

	WARNING: [Synth 8-6014] Unused sequential element cdc_sync_stage1_reg was removed.

To avoid this encase the logic in generate blocks that makes sure they are
not generated when not needed.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-06-06 09:38:19 +02:00
Istvan Csomortani 425e803364 license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
Istvan Csomortani 6a84b8b5a1 license: Update old license headers 2017-07-28 12:53:58 +01:00
Lars-Peter Clausen ab381825da util_cdc: Add event synchronizer
The event synchronizer can be used to safely transfer 1-bit 1-clock cycle
event signals from one clock domain to another.

For each event recorded in the source domain it is guaranteed that a event
will be generated in the target domain at a later point in time. It is
possible though that multiple events in the source domain will be coalesced
into a single event in the target domain if events are generated faster
than they can be transferred.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-23 11:16:07 +02:00