Rejeesh Kutty
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577441bd0c
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daq1: clean up dma interfaces
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2014-09-23 14:23:41 -04:00 |
Istvan Csomortani
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dd7bac41c1
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daq1 : Update project to 2014.2
- Cores are upadted
- Concat module does not swap output anymore
- Clock signal name ps7_clk_* changed to clk_fpga_*
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2014-09-22 17:33:50 +03:00 |
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Istvan Csomortani
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751bdd6cfc
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daq1: Update the constraint file
- tx_ref_clk and rx_sysref need to be differential
- cosmetic changes
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2014-09-19 18:22:57 +03:00 |
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Istvan Csomortani
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a91f4bb6b9
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daq1: General updates
- Add additional GT setups
- Use channel PLL instead of quad PLL
- Add additional ILA probes for debug
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2014-09-13 00:23:11 +03:00 |
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Istvan Csomortani
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ee752ec08a
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daq1: Initial commit
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2014-09-01 18:34:31 +03:00 |