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3417 Commits (46883731eb77b86dd78a0856c1f401f3f7a98a05)

Author SHA1 Message Date
Rejeesh Kutty ca4dca87e2 daq2- updates 2016-10-05 14:02:59 -04:00
Rejeesh Kutty baabe20766 common/zcu102- spi connections & clock 2016-10-05 14:01:59 -04:00
Rejeesh Kutty 39fdf11ef3 util_adxcvr- rx/tx clocks 2016-10-05 13:53:02 -04:00
Istvan Csomortani 7ec93ce8e0 util_adxcvr: Fix some typo 
GTHE4_CHANNEL is instantiated in case of XCVR_TYPE == 2
 2016-10-05 17:42:12 +03:00
Istvan Csomortani 4f587d2e48 util_adxcvr: Delete trailing whitespaces 2016-10-05 17:41:40 +03:00
Istvan Csomortani bab9b2df0b daq3/zc706: Update project with the new transceiver modules 2016-10-05 17:41:25 +03:00
Istvan Csomortani 1b9d2d434c axi_ad9361_tdd: Delete unused register 2016-10-05 17:41:08 +03:00
Adrian Costina c196b5bf68 ad6676evb: VC707, fixed system top gpio_bd datawidth 2016-10-05 15:50:43 +03:00
Adrian Costina ddceff2b5c axi_usb_fx3: Updated header/footer signature 2016-10-04 16:11:24 +03:00
Rejeesh Kutty 48dd4880a3 util_adxcvr- ultrascale+ initial commit 2016-10-03 16:11:45 -04:00
Rejeesh Kutty 0e8551545c util_adxcvr- ultrascale+ initial commit 2016-10-03 16:11:45 -04:00
Rejeesh Kutty b4652650e4 util_adxcvr- xcvr_type parameter 2016-10-03 16:11:45 -04:00
Rejeesh Kutty 63ddcf1e26 util_adxcvr- synthesis warnings fix 2016-10-03 16:11:45 -04:00
Adrian Costina 8e0dc859af axi_usb_fx3: Update 
- added 1 clock delay for slrd_n signal
- rearrange databytes
 2016-10-03 15:17:01 +03:00
Istvan Csomortani 43b3761b80 axi_ad9361: Flop the tx and rx valid 2016-10-03 12:24:04 +03:00
Istvan Csomortani 8e25bc01b3 all: Change tab to double space 
Occasional file parsing and restructuring become a pain, if tabs exists
in code. General rule of the repos is tab always a double space.
 2016-10-01 18:13:42 +03:00
Rejeesh Kutty 0208335ef3 hdlmake- updates 2016-09-30 13:20:22 -04:00
Rejeesh Kutty 27c9bdddb6 daq2/zcu102- 2016.2 updates 2016-09-30 11:55:10 -04:00
Rejeesh Kutty 8e1034946f fmcomms2/zcu102- 2016.2 updates 2016-09-30 11:55:10 -04:00
Rejeesh Kutty 9afff7ae60 common/zcu102- 2016.2 updates 2016-09-30 11:55:10 -04:00
Rejeesh Kutty 33f9ed33c7 projects- ultrascale+ 2016-09-30 11:55:10 -04:00
Rejeesh Kutty 6b956066ef xilinx/ad_lvds*- ultrascale+ 2016-09-30 11:55:10 -04:00
Rejeesh Kutty e9105faae1 library/scripts- add beta devices 2016-09-30 11:55:10 -04:00
Rejeesh Kutty 0ded52d8f6 daq2/zcu102- kcu105 copy 2016-09-30 11:55:10 -04:00
Costina c072c2f89a util_clkdiv: Add IP 2016-09-30 17:13:51 +03:00
Rejeesh Kutty 7290bcc81a hdlmake- updates 2016-09-29 11:50:58 -04:00
Rejeesh Kutty 4950c6c773 adrv9371x - xcvr updates 2016-09-29 11:50:58 -04:00
Rejeesh Kutty 4a5b7fc723 scripts- reconnect added 2016-09-29 11:50:58 -04:00
Rejeesh Kutty ffec95f220 ad9371- xcvr updates 2016-09-29 11:50:58 -04:00
Adrian Costina e40311eee9 adrv9371x: A10soc, connected DMAs through 128 bit SDRAM0 port at 175MHz 2016-09-29 09:14:37 +01:00
Rejeesh Kutty b4fac96aad axi_ad9361- independent disables 2016-09-28 15:45:27 -04:00
Istvan Csomortani f7fb3ccaca axi_ad9361: Change the data path gating 
Bring up the datapath gating from the TDD controller module.
 2016-09-28 16:36:13 +03:00
Istvan Csomortani df485d7878 axi_ad9684: Fix the PN9 PRBS sequence monitor 2016-09-28 10:47:16 +03:00
Rejeesh Kutty 4239f64125 dacfifo- board pin warnings 2016-09-27 14:49:20 -04:00
Rejeesh Kutty 9defccef70 dacfifo- axi address map fixes 2016-09-27 14:48:23 -04:00
Rejeesh Kutty c98e2e95dd ad9162- xcvr updates 2016-09-26 15:21:45 -04:00
Rejeesh Kutty 692cb10fb2 ad9625- xcvr updates 2016-09-26 15:21:11 -04:00
Rejeesh Kutty 751a66eb72 plddr3/zc706- board pin warning 2016-09-26 15:20:37 -04:00
Rejeesh Kutty 79b9e21be8 board- xcvr procedure 2016-09-26 15:20:18 -04:00
Rejeesh Kutty 8314efd4e9 fmcomms11- xcvr updates 2016-09-26 15:19:29 -04:00
Rejeesh Kutty 7fd9280cbf fmcomms11- xcvr updates 2016-09-26 15:19:05 -04:00
Istvan Csomortani ad16aec101 axi_ad9684: Fix SERDES modules 2016-09-26 11:14:35 +03:00
Adrian Costina f5809b8817 adrv9371x: a10soc, added adcfifos; connected the new reset to all peripherals; used the new f2sdram1 port 2016-09-24 10:09:05 +03:00
Adrian Costina 2d307d5f58 a10soc: Added system reset bridge. Using F2SDRAM port used in the previous Qsys design 2016-09-24 10:06:35 +03:00
Rejeesh Kutty f6c7aa9005 library- dac parameter changes 2016-09-23 16:15:59 -04:00
Rejeesh Kutty 1a11e28821 ad9361- dac data path split 2016-09-23 16:13:46 -04:00
Rejeesh Kutty 6735333aea common- dac data path split 2016-09-23 16:13:24 -04:00
Rejeesh Kutty 6837143110 library/ adc parameter changes 2016-09-23 13:44:47 -04:00
Rejeesh Kutty 7be6168b2e ad9361- adc data path split 2016-09-23 13:42:14 -04:00
Rejeesh Kutty 8729af1b91 common- adc- data path disable split 2016-09-23 13:40:35 -04:00