528460371c
axi_ad9963: Updates for ad_dds phase acc wrapper
2018-07-18 18:19:30 +03:00
3b319faef2
axi_ad9963:: Update for CORDIC algorithm
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Add the new files to the IP list
Propagate DDS parameters to top file
2018-07-18 18:19:30 +03:00
dec0661f87
Move Xilinx specific DC filter implementation to library/xilinx/common/
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The DC filter implementation in library/common/dc_filter.v is Xilinx
specific as it uses the Xilinx DSP48 hard-macro. There is a matching Altera
specific implementation in library/altera/common/dc_filter.v.
Move the Xilinx specific implementation from the generic common folder to
the Xilinx specific common folder in library/xilinx/common/ since that is
where all other Xilinx specific common modules reside.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-04-11 15:09:54 +03:00
7d0b162eda
axi_ad9963: Fix port dependency definition
2018-04-11 15:09:54 +03:00
74b922f9f8
axi_*: Infer clock and reset signals of an IP
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A clock sink must be connected to clock source, and a reset sink to
reset source, otherwise the tool will throw a synthesis warning.
By properly inferring all the reset and clock signals of an IP, we can
get rid of unwanted warning messages.
The following IPs tcl script was updated:
- axi_ad9434
- axi_hdmi_tx
- util_cpack
- util_adxcvr
- axi_ad6676
- axi_ad9625
- axi_ad9379
- axi_ad9265
- util_tdd_sync
- util_rfifo
- util_wfifo
- axi_ad9361
- axi_ad9467
- util_upack
- axi_dacfifo
- axi_ad9152
- axi_ad9680
- util_clkdiv
- axi_ad9122
- axi_ad9684
- axi_mc_speed
- axi_mc_current_monitor
- axi_mc_controller
- util_gmii_to_rgmii
- util_adxcvr
- axi_ad9379
- axi_hdmi
- library
- axi_fmcadc5_sync
- util_adcfifo
- util_mfifo
- axi_jesd204_rx
- axi_jesd204_tx
- axi_ad9361
- axi_adxcvr_ip
2018-04-11 15:09:54 +03:00
74ad0d1e46
library: Update
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Older Vivado versions where incorrectly inferring interfaces
-axi_ad9361
-axi_ad9963
-axi_adc_decimate
-axi_adc_trigger
-axi_clkgen
-axi_dac_interpolate
-axi_hdmi_tx
-axi_i2s_adi
-axi_logic_analyzer
-spi_engine
2017-11-15 17:08:45 +02:00
893af8d3e6
library & projects- ad_lvds/ad_data replace
2017-07-26 10:31:48 -04:00
cb4e8f66ef
axi_ad9963: Delete unused source from *_ip.tcl
2017-05-31 18:27:47 +03:00
229829e4dc
axi_ad9963: Add scale only correction option
2017-05-24 15:55:45 +03:00
d43ba5d26e
axi_ad9963: Integrated ADC/DAC clock enables
2017-04-18 12:17:40 +02:00
3ab1e392c5
axi_ad9963: Disable delay_clk port when IODELAYs are unused
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The delay_clk is only used internally when the IODELAYs are enabled. This
means the port has no function when the IODELAYs are disabled so hide the
port in that case.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-18 12:17:40 +02:00
3c13aa49eb
axi_ad9963: Changed TX path from serdes to ddr.
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- remove delay control related logic
2017-04-18 12:17:39 +02:00
9f8fd5c922
axi_ad9963: updated tx path
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- removed pll for power saving, added serdes circuitry instead
2017-04-18 12:17:39 +02:00
c1bdfca4c3
library: Delete all adi_ip_constraint process call
2017-04-06 12:36:47 +03:00
873fbfd6d7
library: Update scripts with new constraints
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Update all IPs tcl scripts with the new constraints files.
Refer to commit 335fef0
2017-03-30 16:16:02 +03:00
fb945ac51c
axi_ad9963: Initial commit
2017-01-31 16:18:58 +02:00
AndreiGrozav
Lars-Peter Clausen
Istvan Csomortani
Adrian Costina
Rejeesh Kutty
Istvan Csomortani