fe92b8b210
axi_ad9671: Updated synchronization mechanism to have a software defined starting code
2014-10-22 13:10:28 +03:00
8934a66013
usdrx1: Update project so that the AD9671 cores can be synchronized
2014-10-13 17:06:40 +03:00
4bdb3cd262
axi_ad9671: altera axi4lite changes
2014-10-09 15:25:07 -04:00
6125bbecc3
axi_ad9671: altera axi4lite changes
2014-10-09 15:25:06 -04:00
2dfcb0c599
usdrx1: Initial commit for a5gt
...
axi_ad9671: added start of frame information to the altera core.
2014-10-07 19:41:54 +03:00
de33722470
up/constr: independent read/write and local constraints
2014-10-02 14:35:59 -04:00
5af2474d51
usdrx1: axi_ad9671 / axi_jesd_gt added signal for frame synchronization
2014-09-23 22:44:33 -04:00
41cc92ef49
Remove BASEADDR/HIGHADDR parameters
...
This is unused and unneeded. The AXI interconnect will make sure that a
peripheral only gets requests that are meant for it, there is no need to
check the address in the peripheral itself.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-09-11 12:26:37 +02:00
50faf0c53a
Remove executable flags from non-exectuable files
2014-09-09 15:05:06 +02:00
da913864c9
ad9671_fmc: updates to match recent core changes
2014-08-28 13:16:52 -04:00
08a12aaf23
library: register map updates on 9467, 9643 and 9671
2014-07-31 15:19:45 -04:00
f55288ef5d
ad9671: altera - base changes
2014-04-28 21:31:18 -04:00
02e8b27626
initial checkin-9250 copy
2014-04-28 21:31:16 -04:00
dfc2bba335
ad9671: updates to allow default adc setup routines
2014-04-23 16:39:28 -04:00
96541f0a7f
usdrx1: zc706 updated for usdrx1
2014-04-10 11:05:13 -04:00
8bebc5e3d4
ad9671: initial checkin
2014-04-07 13:01:10 -04:00
Adrian Costina
Rejeesh Kutty
Lars-Peter Clausen